Six-Stage-Pipelined-Processor

IITB-RISC is a six stage pipelined processor described in VHDL and implemented on an FPGA

This repository contains two parts -

• Part 1: project1 is a six stage pipelined processor
• Part 2: project2 is a six stage pipelined processor with 2-wide fetch

This project is part of Microprocessors (EE309 @EE.IITB)

Team

• Ameya Anjarlekar
• Preetam Pinnada
• Ram Prakash
• Rishi Varrey