Name		Name	Last commit message	Last commit date
dual_port_synchronous_ram		dual_port_synchronous_ram
single_port_synchronous_ram		single_port_synchronous_ram
LICENSE		LICENSE
README.md		README.md

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Synchronous Random Access Memories

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Single Port Snchronous RAM
- single_port_synch_ram.v
Dual Port Synchronous RAM
- dual_port_synch_ram.v

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Random Access Memories designed in Verilog

BSD-2-Clause license

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