AceRoute

AceRoute is a multi-thread parallel FPGA router for FPGA Interchange physical netlists. It implements the ideas from the ICCAD 2024 paper AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration, combining PathFinder-style routing, partition-based inter-connection parallelism, and adaptive intra-connection bidirectional A* exploration to speed up bottleneck connections in congested designs.

How to run

Build via CMake and Ninja. Device file xcvu3p.device is automatically generated and symlinked.

cd AceRoute/
make release   # build the release version

To run the router, you need to provide the paths to input netlists, output netlist, and the config file (optional).

./release/aceroute.exe         \
    -i <input_netlist.phys>    \
    -o <output_netlist.phys>   \
    -c <config.cfg> 

The config can specify all the entries in src/config.h. If not provided, or some entries are not specified, the default values will be used. Here is an example of the config file:

## Config for AceRoute

# If use inter-connection bi-partition parallelism
use_bipartition_par = true

# If use intra-connection bidirectional A* search
use_bidirectional = true

# If use parallel (2-thread) bidirectional search
bidirectional_par = false

# If use adaptive bidirectional search
bidirectional_adapt = true
# Nodes popped as the switching of uni- or bi-directional
ba_switch_nodes_popped = 400
# Or, connection route time (ms) as the switching of uni or bi-directional
ba_switch_route_time = 1

# If specified, record the statistics of each routed connection
connections_log = xxx/log

To run AceRoute on the contest benchmarks, run:

make run-bench BENCHMARKS="<design1> <design2> ..." \  # default: all benchmarks
               CONFIG="path/to/config.cfg"          \
               RESULT_DIR="path/to/result_dir/"     \
               -j <num_parallel_jobs>                  # default: 1

Run with Docker

Refer to AceRoute Reproduction with Docker

Citation

@inproceedings{wei2024aceroute,
  author = {Xinming Wei and Ziyun Zhang and Sunan Zou and Kaiwen Sun and Jiahao Zhang and Jiaxi Zhang and Ping Fan and Guojie Luo},
  title = {AceRoute: Adaptive Compute-Efficient FPGA Routing with Pluggable Intra-Connection Bidirectional Exploration},
  booktitle = {Proceedings of the 43rd IEEE/ACM International Conference on Computer-Aided Design (ICCAD '24)},
  year = {2024},
  pages = {173:1--173:9}
}