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fix(vulkan): declare t10 so the display resolve gets a pipeline #116

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Merged
phobos665 merged 1 commit into from
Nov 2, 2026
Merged

fix(vulkan): declare t10 so the display resolve gets a pipeline #116

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10 changes: 7 additions & 3 deletions src/d3d/rhi_vulkan.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1485,14 +1485,18 @@ static int create_allocator(void)
}

/* The one descriptor set (rhi_vulkan_bindings.h): vertex b0-b3 and b7,
* pixel b0, b1 and b7, t0-t3, t8 and t9, s0-s3, s8 and s9 -- every slot
* the renderer binds (section 4.2). */
* pixel b0, b1 and b7, t0-t3 and t8-t10, s0-s3 and s8-s10 -- every slot
* the renderer binds (section 4.2). A shader that uses any other slot gets
* no pipeline and its draws are skipped (build_pipeline), so a new slot
* goes here when it goes into a shader: t10 is the display resolve's gamma
* ramp (d3d8_display.c), and until it was listed the resolve -- the draw
* that puts each frame on screen -- was skipped on every Vulkan host. */
static const uint32_t g_ubo_bindings[] = {
RHI_VK_VS_UNIFORM_BASE + 0, RHI_VK_VS_UNIFORM_BASE + 1, RHI_VK_VS_UNIFORM_BASE + 2,
RHI_VK_VS_UNIFORM_BASE + 3, RHI_VK_VS_UNIFORM_BASE + 7,
RHI_VK_PS_UNIFORM_BASE + 0, RHI_VK_PS_UNIFORM_BASE + 1, RHI_VK_PS_UNIFORM_BASE + 7,
};
static const uint32_t g_tex_slots[] = { 0, 1, 2, 3, 8, 9 };
static const uint32_t g_tex_slots[] = { 0, 1, 2, 3, 8, 9, 10 };

static int binding_declared(uint32_t binding, uint32_t kind)
{
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