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@ee-uet Department of Electrical Engineering

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    14 repositories

    • UETRV-PCore

      Public
      Linux Capable 32-bit RISC-V based SoC in System Verilog
      VHDL
      •
      Apache License 2.0
      •20•59•0•4•Updated Jun 1, 2026Jun 1, 2026

    • Xce_Training2025_Week02

      Public
      SystemVerilog
      •17•0•0•5•Updated Oct 28, 2025Oct 28, 2025

    • systolic-MAC

      Public
      SystemVerilog
      •
      Apache License 2.0
      •0•2•0•0•Updated Sep 23, 2025Sep 23, 2025

    • Xce_Training2025_Week01

      Public
      C
      •19•0•0•8•Updated Sep 11, 2025Sep 11, 2025

    • Xce_Training2025_Eval01

      Public
      This repository contains the starter files and structure for the first evaluation of Xcelerium Training 2025.
      C
      •19•0•0•10•Updated Sep 11, 2025Sep 11, 2025

    • health-edgeai-mcu

      Public
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Aug 19, 2025Aug 19, 2025

    • UETRV_Pcore_doc

      Public
      Python
      •26•0•0•0•Updated May 13, 2025May 13, 2025

    • UETRV_ESoC

      Public
      Verilog
      •6•19•0•0•Updated Jan 16, 2024Jan 16, 2024

    • fpga-shells

      Public
      Verilog
      •
      Apache License 2.0
      •1•0•0•0•Updated Jul 14, 2023Jul 14, 2023

    • UETRV_ESoC_v2

      Public
      Slightly modified version of UETRV_ESoC, for submission to Google and Efabless' sky130 open mpw-8.
      Verilog
      •
      Apache License 2.0
      •0•1•0•0•Updated Dec 26, 2022Dec 26, 2022

    • UETRV-ECORE

      Public
      Verilog
      •
      Apache License 2.0
      •0•0•0•0•Updated May 6, 2022May 6, 2022

    • Flash_Programmer

      Public
      Assembly
      •0•0•0•0•Updated Apr 25, 2022Apr 25, 2022

    • sermo_soc

      Public
      https://caravel-user-project.readthedocs.io
      Verilog
      •
      Apache License 2.0
      •369•4•0•0•Updated Mar 10, 2022Mar 10, 2022

    • caravel-sermo

      Public
      Scala
      •0•1•0•0•Updated Jun 1, 2021Jun 1, 2021
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