I have implemented a DMA-like accelerator, and I am in the process of writing a kernel driver to control it from user space.
I need to clear the processor's cache so my user process does not read outdated data. When I previously tested my accelerator with a bare-metal program, I used the following macro:
#define FLUSH_D_CACHE() ({__asm__ volatile("csrwi 0x7C1, 0x00"); \
__asm__ volatile("csrwi 0x7C1, 0x01");})But it uses machine-level CSRs, which of course causes an illegal instruction exception when ran inside a kernel module.
How can I do this? According to this, support for cache clearing is limited.
If the software route does not work out, I suppose there is a way to flush the data cache in hardware. I could maybe route a signal from my accelerator to the cache subsystem that forces a cache flush. Any ideas?
I have implemented a DMA-like accelerator, and I am in the process of writing a kernel driver to control it from user space.
I need to clear the processor's cache so my user process does not read outdated data. When I previously tested my accelerator with a bare-metal program, I used the following macro:
But it uses machine-level CSRs, which of course causes an illegal instruction exception when ran inside a kernel module.
How can I do this? According to this, support for cache clearing is limited.
If the software route does not work out, I suppose there is a way to flush the data cache in hardware. I could maybe route a signal from my accelerator to the cache subsystem that forces a cache flush. Any ideas?