fix: initialize the last 4 bytes of mem to zero#149
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These last 4 bytes are, in fact, used for register `x0`, and must be zero. In multi-valued simulators, however, without an explicit init, these bytes start as undefined. Moving `x0` to anywhere results in those undefined bytes "infecting" other registers. Issue: olofk#148
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Hi, I know this PR is sort of old, but I just came back to the project and saw this. I fully agree with your assessment, and I'm kind of surprised that this isn't giving us trouble in synthesis as well, as the RAM could be initialized to a value other than My only question here is: Have you looked into how different synthesis tools handle this way of resetting the bits to zero? Are they still able to map it to an EBR? (Pretty sure Vivado can do it, but not sure about others.) |
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Vivado seems to do the right thing, that's all I know, since I can only use
Vivado: that's the default for my Xilinx devices, and all other synthesis
tools hav been eaten by the Big Three, and they won't sell licenses to
individuals. :/ So...
…On Tue, May 5, 2026 at 5:40 PM Markus ***@***.***> wrote:
*m42uko* left a comment (olofk/serv#149)
<#149 (comment)>
Hi, I know this PR is sort of old, but I just came back to the project and
saw this.
I fully agree with your assessment, and I'm kind of surprised that this
isn't giving us trouble in synthesis as well, as the RAM could be
initialized to a value other than 0 there as well (depending on the
architecture). So I think adding some kind of logic like this is definitely
a good idea.
My only question here is: Have you looked into how different synthesis
tools handle this way of resetting the bits to zero? Are they still able to
map it to an EBR? (Pretty sure Vivado can do it, but not sure about others.)
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These last 4 bytes are, in fact, used for register
x0, and must be zero. In multi-valued simulators, however, without an explicit init, these bytes start as undefined. Movingx0to anywhere results in those undefined bytes "infecting" other registers.Issue: #148