AMDFamily17, IntelMSR: allow hardware-prefetcher / cache configuration MSRs

[yuzi-co]

This adds the documented hardware-prefetcher, load-store, and cache configuration MSRs to the
AMDFamily17 and IntelMSR allow-lists so they can be read and written for CPU tuning — the same
kind of thing the modules already expose for P-state / HWCR / power-limit registers.

What changed

AMDFamily17.p — added to both is_allowed_msr_read and is_allowed_msr_write:

MSR	Addr	AMD PPR name
MSR_LS_CFG	0xC0011020	Load-Store Configuration
MSR_IC_CFG	0xC0011021	Instruction Cache Configuration
MSR_DC_CFG	0xC0011022	Data Cache Configuration
MSR_LS_CFG2	0xC001102B	Load-Store Configuration 2

(AMD PPR for family 17h–1Ah; these registers hold the hardware prefetcher and speculation controls.)

IntelMSR.p — added to both allow-lists:

MSR	Addr	Intel SDM name
MSR_MISC_FEATURE_CONTROL	0x1A4	Misc. feature control — L2 HW / adjacent-line / DCU / DCU-IP prefetcher enables (bits 0–3)

Why

These are the standard, vendor-documented registers for toggling the hardware prefetchers and
related load/store behaviour. They're useful for tuning memory-latency-sensitive workloads, where
the prefetchers can hurt throughput on random-access patterns. Right now there's no signed way to
touch them on a modern (Secure Boot / HVCI) Windows box without an unsafe WinRing0-style driver —
which is exactly what PawnIO is meant to replace.

Safety / scope

• Gated through the existing is_allowed_msr_read / is_allowed_msr_write switches — no arbitrary
  MSR access is introduced; only these specific, documented config registers are permitted, exactly
  as the modules already gate writes to the P-state, HWCR, CSTATE, CPPC, and power-limit MSRs.
• AMD reads are additionally gated by the module's existing family 0x17–0x1A check; Intel by the
  CpuVendor_Intel check.
• No new IOCTLs, no new natives, no behavioural change to existing reads/writes. LGPL-2.1, no new
  warnings.

Happy to adjust naming, split the AMD/Intel changes, or narrow the set if you'd prefer.