Skip to content
View mukundan1012-creator's full-sized avatar

Block or report mukundan1012-creator

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Hi, I'm Mukundan πŸ‘‹

B.E Electronics and Communication Engineering Β |Β  Building toward ML / Embedded / VLSI roles at chip companies

I combine machine learning depth with embedded systems and digital logic design β€” three areas that rarely overlap in a single student's portfolio, but all matter directly to how modern chip companies build products.


πŸš€ Projects

πŸ›‘οΈ AI-Powered SMS Phishing Detection TF-IDF + Logistic Regression spam/phishing classifier β€” 99.01% accuracy, 95% recall, ROC-AUC 0.9959. Includes an honest false-negative analysis and a "what I'd rebuild" retrospective.

πŸ“Š Student Performance Predictor Random Forest regressor predicting final grades β€” RΒ² = 0.86. Includes a deliberate honesty check showing RΒ² drops to 0.16 without prior-grade features, confirming what the model actually learns.

🌑️ Smart Environmental Monitor ESP32 + BMP180 sensor system using I2C and a non-blocking state machine, with a Python serial logger writing to CSV. Capstone of a 14-day embedded systems roadmap.

πŸ”§ VLSI CPU Datapath 11-day Verilog progression from logic gates to a working Mini CPU Datapath (8-bit ALU, control FSM, registers, flags), simulated with Icarus Verilog and GTKWave. Documents a real clock-edge race condition, found and fixed.


πŸ“š Currently Learning

SQL β†’ Python β†’ Machine Learning (through SHAP) β†’ C++ β†’ Embedded Systems β†’ TinyML/Edge AI followed by a VLSI Flow Track: RTL β†’ Verification β†’ Synthesis β†’ Static Timing Analysis β†’ Physical Design


πŸ“« Contact

LinkedIn Β· Email: mukundan1012@gmail.com

Popular repositories Loading

  1. StudentPerformancePredictor_Final StudentPerformancePredictor_Final Public

    An end-to-end Machine Learning web Apllication built with a Random Forest Regressor and Streamlit to predict final student grades

    Jupyter Notebook

  2. AI-SMS-Phishing-Detection AI-SMS-Phishing-Detection Public

    Machine Learning based SMS Phishing Detection using TF-IDF, Feature Engineering and Logistic Regression

    Jupyter Notebook

  3. Smart-Environmental-Monitor Smart-Environmental-Monitor Public

    ESP32 + BMP180 environmental monitor with I2C, state machine, and Python logging

    C++

  4. vlsi-cpu-datapath vlsi-cpu-datapath Public

    11-day Verilog/VLSI sprint: from logic gates to a Mini CPU Datapath (8-bit ALU, control FSM, registers, flags) β€” built and simulated with Icarus Verilog + GTKWave

    Verilog

  5. mukundan1012-creator mukundan1012-creator Public

  6. Drug_Demand_Forecaster Drug_Demand_Forecaster Public

    Drug Demand Forecaster β€” ARIMA vs Prophet per-category auto-selection across 8 ATC drug categories

    Jupyter Notebook