feat: enable topology discovery and memory transfer with AMD GPUs with verbs;ofi_rxm provider on 8xMI300X machine#7
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Extends the Libfabric plugin's topology discovery and rail selection to support AMD MI300X systems with InfiniBand/RoCE NICs (Broadcom bnxt_re, Mellanox ConnectX). Previously, topology-aware rail building only worked for AWS EFA devices. This PR adds:
isInfiniBandDevice()method recognizes Mellanox HCAs (vendor0x15b3, class0x0c06) via hwlocverbs;ofi_rxmprovider support — topology discovery, PCIe mapping, and rail building now handle the verbs RDM provider alongside EFA/CXITesting
Tested with
libfabric_topology_testwhich executes 9 sub-tests: 1 topology query + 8 bandwidth scenarios. All pass. I run three tests:With the real hwloc information on the 8xMI300x machine:
NIXL_LOG_LEVEL=TRACE ./build/test/unit/utils/libfabric/libfabric_topology_test mi300xLog file: libfabric_topology_test.log.zip Total: 364,536 TRACE-level log lines.With the mock hwloc XML colected from the same machine:
cd test/unit/utils/libfabric/topo ../../../../../build/test/unit/utils/libfabric/libfabric_topology_test mi300xWith the complete set of XML mocks from the repo:
cd test/unit/utils/libfabric/topo ../../../../../build/test/unit/utils/libfabric/libfabric_topology_testReal hwloc information on the 8xMI300x machine
Phase 1: Topology Query for DRAM_SEG Rail Count (lines 1–429)
Validates that the topology engine computes the correct number of rails per NUMA node.
Testing topology query for DRAM_SEG NUMA-aware rail selection on instance type mi300xhwloc topology initialized successfully with IO device support[TEST] Found OS device: bnxt_re0..7, mlx5_0, mlx5_1(10 OpenFabrics devices via hwloc)Found device - domain: bnxt_re5, provider=verbs;ofi_rxm(×10 devices)Discovered 10 InfiniBand (verbs;ofi_rxm) devicesMapped PCIe 0:a3:00.0 → Libfabric bnxt_re5 (NIC link speed: 400000000000)(×10)Found AMD accelerator: 0:05:00.0 (vendor=0x1002, device=0x74a1, class=0x1200)(×8 MI300X GPUs)Discovered 0 NVIDIA, 8 AMD, and 0 Neuron accelerators via hwlocNIC at PCIe address 0:23:00.0 is closest to NUMA node 0— 6 NICs on NUMA 0, 4 on NUMA 1NUMA node 0 capacity is 2020 Gbps/NUMA node 1 capacity is 2020 GbpsNIC bandwidth is uniform across all PCIe devices with bandwidth: 400 GbpsNon-uniform NIC mlx5_0 upstream link speed: 252 Gbps, expecting 504 Gbps(mlx5 behind narrower PCIe link)Accelerator-PCI 0:c7:00.0 → [bnxt_re6](×8 GPU-to-NIC mappings)SUCCESS: Topology calculated correct rail count 4 for DRAM_SEG NUMA-aware rail selection policyPhase 2–9: Bandwidth Scenario Tests (lines 430–364,536)
Each scenario re-discovers topology, then runs single-threaded + multi-threaded rail selection validation at a specific bandwidth target. Bandwidth determines how many rails are needed.
Each scenario follows the same internal flow:
Closing endpoint/CQ/AV/domain/fabric for rail N)Final line:
Test scenario [bandwidth=4000] on instance type mi300x SUCCESS/=== Test completed successfully! ===Topology file
Topology XML file was generated using following snippet:
And then
gcc export_topo.c -lhwloc -o export_topo && ./export_topoProbably the same can be achieved with
lstopo --of xml mi300x-topo.xml