In this project, I designed and implemented a parameterized Arithmetic Logic Unit (ALU) using Verilog HDL. The goal of this project was to understand how arithmetic and logical operations are implemented in hardware and how these operations form the core of a processor's datapath.
The ALU performs multiple arithmetic, logical, and shift operations based on a select signal. The design also generates standard processor status flags such as Carry, Zero, Negative, and Overflow. These flags are important in real processors because they indicate the result condition of operations.
To make the design more flexible and reusable, the ALU was implemented using parameterized bit width, which allows the same design to work for different data sizes such as 8-bit, 16-bit, or 32-bit systems.
The main objectives of this project were:
- To design a multi-operation ALU using Verilog HDL
- To implement arithmetic, logical, and shift operations
- To generate status flags used in processor architectures
- To create a parameterized and modular hardware design
- To verify the design using a self-checking testbench and simulation waveforms
The ALU takes two input operands and performs operations depending on the value of a select signal.
Inputs:
- A – First operand
- B – Second operand
- sel – Operation selector
Outputs:
- result – Output of the selected operation
- status flags – Carry, Zero, Negative, Overflow
The basic working principle is that the select signal determines which operation is performed on the input operands.
The ALU supports several arithmetic, logical, and shift operations.
| Select (sel) | Operation |
|---|---|
| 0 | Addition |
| 1 | Subtraction |
| 2 | AND |
| 3 | OR |
| 4 | XOR |
| 5 | NOT |
| 6 | Shift Left |
| 7 | Shift Right |
| 8 | Rotate Left |
| 9 | Rotate Right |
These operations represent the basic functionality present in the arithmetic logic units of many processors.
The ALU generates four important flags that are commonly used in processor architectures.
Carry Flag (C) Indicates a carry generated during arithmetic operations.
Zero Flag (Z) Set when the result of an operation is zero.
Negative Flag (N) Indicates that the result is negative (based on the most significant bit).
Overflow Flag (V) Indicates signed arithmetic overflow when the result exceeds the representable range.
These flags help control decision-making operations in processors such as conditional branching.
The design includes shift operations which are implemented using a barrel shifter concept.
A barrel shifter allows shifting or rotating bits in a single operation. This is commonly used in processors for fast bit manipulation operations such as:
- Logical shifts
- Rotations
- Bit-level transformations
One important feature of this ALU is that it is parameterized. This means the bit width of the ALU can be easily modified by changing a parameter in the code.
Example:
parameter N = 8;By modifying this value, the ALU can be converted into a 16-bit or 32-bit ALU without changing the rest of the design.
This makes the hardware design scalable and reusable.
To verify the functionality of the ALU, I developed a Verilog testbench.
The testbench performs the following tasks:
- Provides different input values to the ALU
- Changes the select signal to test different operations
- Observes the output results and flags
- Generates simulation waveforms
The simulation results were analyzed using waveform viewers to ensure that the ALU operates correctly for all supported operations.
verilog-alu-datapath
│
├── alu.v
├── alu_tb.v
├── register_file.v
├── waveform_alu.jpeg
└── README.md
alu.v – Contains the main ALU design alu_tb.v – Testbench used for simulation and verification register_file.v – Register module used for storing operands waveform.jpeg – Simulation waveform showing ALU behavior
The following tools were used during the development and simulation of this project:
- Verilog HDL
- ModelSim / Vivado Simulator / Icarus Verilog
- GTKWave (for waveform visualization)
The ALU is a fundamental building block in digital systems and is widely used in:
- CPUs and microprocessors
- Embedded systems
- Digital signal processing units
- FPGA-based processors
Understanding the design of an ALU provides insight into how processors execute instructions internally.
This project helped me gain practical experience in digital hardware design using Verilog HDL. I learned how arithmetic and logical operations are implemented at the hardware level, how processor status flags are generated, and how simulation is used to verify hardware functionality.
The parameterized and modular approach used in this design makes the ALU flexible and suitable for integration into larger digital systems such as processor datapaths.