32-Bit Multi-Cycle CPU Design in VHDL

A 32-bit multi-cycle processor developed in VHDL, simulated using ModelSim for the Altera Cyclone IV DE2-115 FPGA. This project was made as part of a series of in-class labs for COE 608 and expands on digital design principles from COE 328 (Check out the 8-Bit CPU) to implement a RISC-style instruction set with dedicated data and control paths.

Overview

This processor consists of a Harvard load-store architecture with separate instruction and data memory spaces. All instructions are 32 bits long and require a 4-byte memory word. Instruction execution is handled in three clock cycles ( $T_0, T_1, T_2$ ).

Key Architectural Features

• Buses: 32-bit external data bus, 16-bit instruction bus, and an 8-bit data memory bus.
• Memory: Supports 256B of Instruction Memory (16-bit address) and 1KB Data Memory.
• Execution: Multi-cycle instruction execution with a simple instruction set. All data operations happen within the registers.

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Instruction Set & Opcodes

The CPU uses two primary instruction formats: Memory Addressing/Immediate words and Data Processing words. Data processing instructions are explicitly denoted when the upper 4 bits (IR[31..28]) are set to 0111.

Memory Addressing & Control Flow

Mnemonic	Opcode (IR[31..28])	Function
LDAI	0000	A <= IR[15:0]
LDBI	0001	B <= IR[15:0]
STA	0010	M[ADDRS] <= A, ADDRS <= IR[15:0]
STB	0011	M[ADDRS] <= B, ADDRS <= IR[15:0]
LUI	0100	A[31:16] <= IR[15:0], A[15:0] <= 0
JMP	0101	PC <= IR[15..0]
BEQ	0110	IF(A==B) then PC <= IR[15..0]
BNE	1000	IF(A!=B) then PC <= IR[15..0]
LDA	1001	A <= M[ADDRS], ADDRS <= IR[15:0]
LDB	1010	B <= M[ADDRS], ADDRS <= IR[15:0]

Data Processing (IR[31..28] = 0111)

Mnemonic	Function Code (IR[27..24])	Function
ADD	0000	A <= A + B
ADDI	0001	A <= A + IR[15..0]
SUB	0010	A <= A - B
INCA	0011	A <= A + 1
ROL	0100	A <= A << 1
CLRA	0101	A <= 0
CLRB	0110	B <= 0
CLRC	0111	C <= 0
CLRZ	1000	Z <= 0
ANDI	1001	A <= A AND IR[15..0]
TSTZ	1010	If Z = 1 then PC <= PC + 1
AND	1011	A <= A AND B
TSTC	1100	If C = 1 then PC <= PC + 1
ORI	1101	A <= A OR IR[15..0]
DECA	1110	A <= A - 1
ROR	1111	A <= A >> 1

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Components

1. Control Unit (Control_New.vhd)

Decodes instruction opcodes for state transitions. Coordinates the multi-cycle timing:

• $T_0$ (Instruction Fetch 1): Instruction address from the PC is transferred to the IR.
• $T_1$ (Fetch 2 & Pre-decode): Increments the PC and asserts setup signals (en and wen) necessary for Load/Store operations.
• $T_2$ (Decode & Execute): Executes operations and asserts correct MUX timings.

2. Register Set

• User-Visible Registers: Two 32-bit working registers (A and B) and two 1-bit status registers (C for Carry, Z for Zero).
• Internal Registers: 32-bit Program Counter (PC) and Instruction Register (IR).

3. Reset Circuitry (reset_circuit.vhd)

Makes sure that the CPU begins in a stable state. When the RESET signal goes high, ENABLE_PD is forced low (returning the Control Unit to $T_0$) and CLR_PC goes high to clear the Program Counter.

4. Memory Blocks

• Instruction Memory: Implemented using a MegaCore RAM block (.mif).
• Data Memory: 1KB data memory supporting setup/hold timings during $T_1$ and $T_2$ states.

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Hardware Specifications

• Target Device: Altera Cyclone II EP2C35F672C6 (Altera DE2 Development Board)
• Design Paradigm: Multi-Cycle (3 clock cycles per instruction)
• Architecture: Harvard Load/Store

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Build Instructions

What You Need

• Quartus II 13.0
• ModelSim-Altera for simulation
• Altera Cyclone II EP2C35 FPGA board for hardware emulation

FPGA Deployment Steps

1. Clone this repository.
2. Open Quartus II: Launch Quartus II 13.0 and open the .qpf project file.
3. Set Top-Level Entity: Set the overall CPU assembly file as the top-level entity.
4. Compile the design: Go to Processing → Start Compilation (or press Ctrl+L).
5. Program the FPGA: Connect the DE2 board via USB Blaster, open Tools → Programmer, load the .sof file, and start programming.

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Simulation & Verification

1. Open ModelSim: From Quartus, navigate to Tools → Run Simulation Tool → RTL Simulation.
2. Load Testbench: Use the testbenches located in the simulation directory and use the provided Memory Module files.
3. Run Timing Simulation: Make sure that the CPU accurately fetches instructions across $T_0 \rightarrow T_1 \rightarrow T_2$ transitions and executes LDA, LUI, addition, and branching operations properly.

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Course Information

• Course: COE 608 — Computer Organization and Architectures
• Institution: Toronto Metropolitan University
• Instructor: Dr. Vadim Geurkov
• Semester: Winter 2026

Acknowledgments

• TMU Department of Electrical, Computer, and Biomedical Engineering
• Dr. Vadim Geurkov for course instruction
• T.A. Nathan Vu for lab support
• Altera Quartus II and ModelSim

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