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miesource/README.md

Hi, I'm Ihab

Building secure, high-performance hardware from the ground up.

About Me

  • FPGA engineer
  • Interested in cryptography and hardware security
  • Building hardware accelerators, Python models for hardware verification and FPGA workflows
  • Working primarily with VHDL, Python and TCL

Projects Done

  • ECC Hardware Accelerator over NIST B-233 DOI

  • ECC Hardware Accelerator over NIST P-256 DOI

  • AXI4-Lite wrapped ML-KEM NTT Accelerator (FIPS 203) DOI

Elsewhere

Featured Repositories

ecc_hardware_accelerator_NIST-B233

  • NIST B-233 Elliptic Curve Cryptography Scalar Multiplication
  • Modified Lopez-Dahab coordinates
  • UART-connected FPGA accelerator in Artix-7

ecc-hardware-accelerator-NIST-P256

  • NIST P-256 Elliptic Curve Cryptography Scalar Multiplication
  • Constant-time Montgomery ladder
  • AXI4-Lite wrapped FPGA accelerator in Kria K26

ntt-hardware-accelerator-mlkem

  • Forward NTT, inverse NTT, and pointwise multiplication cores to accelerate polynomial arithmetic for NIST’s FIPS 203 (ML-KEM / CRYSTALS-Kyber) standard.
  • Incomplete 7-layer NTT with bit-reversed twiddle addressing.
  • Integrated a dedicated memory sequencer and custom Montgomery reduction multiplier.

Pinned Loading

  1. ntt-hardware-accelerator-mlkem ntt-hardware-accelerator-mlkem Public

    AXI4-Lite wrapped forward NTT, inverse NTT , and pointwise multiplication cores to accelerate polynomial arithmetic for NIST’s FIPS 203 (ML-KEM / CRYSTALS-Kyber) standard.

    VHDL 2

  2. ecc_hardware_accelerator_NIST-B233 ecc_hardware_accelerator_NIST-B233 Public

    NIST B-233 Elliptic Curve Cryptography Scalar Multiplication Hardware Accelerator using Modified Lopez-Dahab Projective Coordinates and communicates over UART

    VHDL 2

  3. ecc-hardware-accelerator-NIST-P256 ecc-hardware-accelerator-NIST-P256 Public

    AXI4-Lite wrapped high-performance ECC hardware accelerator for the NIST P-256 with side-channel attacks resistance.

    VHDL 1