Email: muhammadfaizanm00@gmail.com
Phone: +92 (340) 7663425
I am a Design Engineer specializing in FPGA and RTL development for image signal processing (ISP) and custom hardwares. Currently, I contribute to the open-source Infinite-ISP project and develop industrial‑standard HDR‑ISP pipelines on Xilinx and Efinix platforms. With a solid foundation in SystemVerilog, Verilog, and RISC‑V, I thrive on solving complex digital design challenges and optimizing performance at both hardware and firmware levels.
- Languages: SystemVerilog, Verilog, Python, C, TCL scripting, Makefile
- Tools & Frameworks: Xilinx Vivado & Vitis, Efinix Efinity, QuestaSim, ModelSim, Quartus Prime, Git, Cocotb
- Domains: FPGA Design & Integration, HDR & SDR Image Signal Processing, Digital Systems Design, RTL Verification
- AXI4‑Lite Interface for Infinite‑ISP: Enabled efficient register access and control for ISP pipelines.
- Sharpening Module for Infinite‑ISP: Designed RTL module to enhance edge clarity and texture details.
- Infinite‑ISP FPGA Integrations: Integrated ISP cores on multiple FPGA platforms with various image sensors.
Check out my work: github.com/mfaizan-7
- OpenRoad Triton Router Optimization: Improved routing runtime using compiler intrinsics and ISPC.
- RISC‑V 3‑Stage Pipelined Processor: Implemented privilege support and CSRs for trap handling in Verilog.
- 16‑bit Multiplier (Russian‑Peasant Algorithm): Developed datapath and control logic in Verilog.
- UART Transmitter (SystemVerilog): Created module managing start/stop bits and parity for UART communication.
B.Sc. Electrical Engineering
University of Engineering and Technology Lahore, Pakistan
Relevant Coursework: Computer Architecture, Digital Systems Design, VLSI, Computer Networks, Digital Signal Processing, Programming Fundamentals, Calculus, Linear Algebra