ARM Single-Cycle Processor (Verilog Implementation)

This project is a Verilog implementation of an ARM single-cycle processor, based on the architecture described in Harris & Harris's Digital Design and Computer Architecture. It was developed as part of the EE446 course at Middle East Technical University (METU).

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Features

This processor implements a single-cycle ARM datapath and supports the following instruction set:

Instruction Set (ISA)

• Arithmetic & Logic:
  • ADD, SUB, AND, ORR, CMP
• Data Movement:
  • MOV (register), MOV (immediate)
• Memory Access:
  • STR, LDR
• Control Flow:
  • B, BL, BX

Extended Instructions

Additional instructions beyond the base design:

• CMP (compare without storing result)
• BX (branch and exchange)
• BL (branch with link — used for subroutines)

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Module Overview

Key modules implemented in Verilog include:

• Datapath.v – Main datapath with ALU, register file, and memory interface
• ALU.v – Arithmetic Logic Unit
• Controller.v – Generates control signals based on opcode
• Register_file.v – 16-register bank with read/write support
• Memory.v – Data memory
• Instruction_memory.v - Instruction memory
• Mux*.v – Multiplexers (2-to-1, 4-to-1, etc.)
• shifter.v – Logical shift left/right unit
• MSSD.v – seven segment display module for nexys a7 fpga board.

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Testing and Simulation

The processor was tested using Cocotb testbenches and synthesized for functionality on FPGA (Nexys A7 board).

• Functional simulation with ModelSim / Icarus Verilog
• Inputs: switches and buttons
• Outputs: seven-segment displays for observing results

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