Name		Name	Last commit message	Last commit date
.gitignore		.gitignore
IR.vhd		IR.vhd
IR_test.vhd		IR_test.vhd
PC.vhd		PC.vhd
PC_test.vhd		PC_test.vhd
README.md		README.md
WP.vhd		WP.vhd
WP_test.vhd		WP_test.vhd
addressLogic.vhd		addressLogic.vhd
addressLogic_test.vhd		addressLogic_test.vhd
addressingUnit.vhd		addressingUnit.vhd
addressingUnit_test.vhd		addressingUnit_test.vhd
alu.vhd		alu.vhd
alu_test.vhd		alu_test.vhd
controller.vhd		controller.vhd
controller_test.vhd		controller_test.vhd
datapath.vhd		datapath.vhd
datapath_test.vhd		datapath_test.vhd
flags.vhd		flags.vhd
flags_test.vhd		flags_test.vhd
memory.vhd		memory.vhd
memory_test.vhd		memory_test.vhd
registerFile.vhd		registerFile.vhd
registerFile_test.vhd		registerFile_test.vhd
sayeh.vhd		sayeh.vhd
sayeh_test.vhd		sayeh_test.vhd

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SAYEH Basic Computer

SAYEH basic computer implementation in VHDL.

TODOs

Zin & Cin in ALU are not used
Implement effectiveAddress and writeBack states for controller
How could I (Immediate) be written on Databus?

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SAYEH Basic Computer in VHDL

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