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P0 Studio field fixes: delayed USB firmware verification, truthful START, capture phase evidence - #259
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…existing PCAP evidence
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…o lost early click
…en with 0 packet loss
… blocks acceptance
…ld fail-closed cases
2026-10-23 source parity audit vs recovered checkpoint — KEEP OPENSource #259 head Historical #259 had specific physical evidence (flash verified much later than immediate USB IDENTIFY, exact c959... found) and a fail-closed post-flash identity wait. Unique release gate: write-bin success followed by USB CDC delay must not generate a false failed-flash/reflash or Disposition: KEEP OPEN, not obsolete, until deliberately ported/retested into selected Stage→Main source or explicitly descoped with maintainer approval. No code copied, no branch changed, and no merge. |
Physical evidence 2026-10-20
On-board ESP32-P4 v1.3, write-bin and reset succeeded but immediate serial IDENTIFY timed out. Later PCAP Studio telemetry showed exact bundled build c959486 running, so flash was written; UI incorrectly reported a terminal failure. At the same time ~125s on-wire SV sample sequence was continuous (499,696 packets, 3,999.900 fps, missing=0, duplicate=0, malformed=0), while smpSynch went 0→1→0→1. PTP SOURCE packet presence does not prove external GM lock and all Studio snapshots reported UNLOCKED; release stays blocked.
Corrections
Previewcontrol only in stable offline state; while a real board is CONNECTING/awaiting identity, the physical START cannot silently become offline preview. Keep transactional START/ACK validation and visible Starting state.Release gate
Do not merge main until exact-head CI passes and post-fix physical re-test demonstrates serial recovery, single-click START, and no transient LOCAL drops with IED/GM acceptance.