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P3-H P0.1: encoder-produced deterministic SV WirePlan - #141

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masarray merged 2 commits into
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hardening/smv-p0-1-wireplan
Oct 6, 2026
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masarray merged 2 commits into
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hardening/smv-p0-1-wireplan

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@masarray masarray commented Oct 6, 2026

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Stacked on #140. Tracks #139.

Base head expected: a09e0312dd1257404669ddc2e6a2cf4264d072a6
This PR must not merge before #140 is accepted; after #140 lands, retarget/re-evaluate against current main.

Why

The deterministic ESP32-P4 publisher still rediscovered smpCnt, confRev and seqData offsets by scanning the fully encoded frame for tag/length byte patterns. Separately, the smpSynch TX interception shim structurally parsed BER on every transmitted SV frame and contained a second canonical transport-failure guard even though app_main.cpp already owns that failure policy.

That is correctable technical debt in the realtime path.

Architecture change

  • SampledValuesPduCodec::encode_into_with_layout()
    • records patchable ASDU value regions at the exact moment BER bytes are written;
    • caller supplies std::span<SampledValueAsduEncodeLayout>; no metadata heap allocation;
    • layout is naturally per-ASDU and therefore multi-ASDU-ready.
  • SampledValuesFrameCodec::encode_into_with_layout()
    • preserves the same encoded bytes;
    • translates PDU-relative regions into absolute Ethernet-frame offsets.
  • ESP template build consumes this metadata once while STOPPED.
  • Realtime publisher patches smpCnt, smpSynch and seqData directly by bounded offsets.
  • The compile-time TX interception macro and per-transmit BER scan are removed.
  • The duplicate transport-failure guard in smp_synch_lab.cpp is removed; app_main.cpp remains the single canonical TX failure authority.
  • The existing structured wire_field_offsets.hpp utility remains available for inspection of arbitrary/foreign frames; it is no longer part of deterministic publication.

Runtime properties

No XML/SCL parsing, BER parsing, packet rescanning, dynamic re-encoding or new allocation is added to the steady-state publish loop.

Per published sample, synchronization policy resolves from atomics and the selected value is a direct one-byte patch. Canonical/mirror frames use the same decision for that sample.

Regression coverage

  • layout encoding produces byte-for-byte identical output to existing encode paths;
  • frame-relative offsets are validated for VLAN and untagged frames;
  • field presence/absence is validated for optional ASDU fields;
  • two-ASDU layout is validated and both smpCnt fields can be patched independently then decoded correctly;
  • insufficient caller layout storage fails closed;
  • current bounded firmware still requires exact widths: smpCnt=2, confRev=4, smpSynch=1, seqData=64.

Non-goals

No IEC 61869-9 profile expansion, no arbitrary dataset activation, no multi-stream scheduler, no PTP conformance claim and no PRP/HSR work in this PR.

Next node after P0/P0.1: #139 P1 timing/profile semantic separation.

Record ASDU field regions while BER is encoded, translate them to absolute Ethernet offsets, and consume those offsets directly in the ESP32-P4 publisher. Remove per-transmit smpSynch BER scanning and the duplicate transport-failure guard so the realtime path has one TX authority. Tracks #139.
Reject reintroduction of raw fixed-field scans, TX interception, smpSynch wire parsing, or a second transport-failure authority in the ESP32-P4 publication path. Tracks #139.
@masarray
masarray changed the base branch from hardening/smv-p0-standards-invariants to main October 6, 2026 12:43
@masarray
masarray marked this pull request as ready for review October 6, 2026 12:44
@masarray
masarray merged commit f3a107e into main Oct 6, 2026
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📝 Code Review ✅ Completed 2026-10-06T12:48:13.281940Z d63cec7 Draft marked ready
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