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P3-H P1.2: IEC 61869-9 variant, dataset and scaling authority #144

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Description

@masarray

Purpose

Continue #139 after P1.1 / #143 is accepted.

Build an explicit IEC 61869-9 variant + channel scaling authority without turning current vendor limits or ESP32-P4 constraints into protocol-standard rules.

This issue is coordination-only until #143 is merged. Do not branch P1.2 from a pre-P1.1 base.

Standards/evidence boundary

Current published baseline:

  • IEC 61869-9:2016 is the published product-family standard for digital instrument-transformer interfaces.
  • IEC 61850-9-2 Ed2.1 remains the SV transport/mapping layer.
  • IEC 61869-9 AMD1 is still draft/CDV work in 2026. Its SynchSrcID and slew-synchronization additions must be representable but must not be claimed as current published conformance.

Observed interoperable implementations confirm that IEC 61869-9 is not one fixed 4I+4V packet:

  • F4800S2 and F14400S6 are deployed profiles.
  • configurable AmpSv/VolSv channels are used by current relays/MUs.
  • vendor limits such as 24 or 32 channels are product capability, not generic standard limits.

Single-authority model

Introduce one standards-owned IEC 61869-9 profile description containing:

  • explicit FfSsIiUu variant identity: sample rate, ASDUs per message, current quantity count and voltage quantity count;
  • explicit sampling/packetization variant;
  • exact rational sample/frame cadence (reuse P1 timing authority);
  • channel semantic: Current / Voltage;
  • INT32 engineering representation;
  • exact rational engineering scale, never hidden floating-point constants;
  • required measurement + corresponding Quality pairing;
  • ordered dataset binding;
  • synchronization/profile requirements and optional-field capability;
  • published-standard vs draft/future feature status.

Do not infer semantic from vendor, filename, svID, DataSet name, or UI labels.

Scaling authority

For the normal IEC 61869-9 current/voltage sampled-value representation, model the standardized quantization explicitly:

  • current: 1 mA/count;
  • voltage: 10 mV/count.

Represent scales as rational integer metadata, e.g. numerator/denominator, so waveform generation and encode/decode remain deterministic and unit-safe.

Do not hard-code these numbers inside the waveform engine or GUI.

Variant authority

Model standard sampling/packetization combinations independently from device support.

At minimum cover the published IEC 61869-9 families used in current interoperability literature:

  • 4000 samples/s, 1 ASDU/frame;
  • 4800 samples/s, 1 ASDU/frame;
  • preferred F4800S2;
  • 5760 samples/s, 1 ASDU/frame;
  • 12800 samples/s, 8 ASDUs/frame;
  • preferred F14400S6;
  • 15360 samples/s, 8 ASDUs/frame;
  • 96000 samples/s, 1 ASDU/frame / wideband family.

The authority must distinguish:

  1. recognized IEC 61869-9 variant,
  2. preferred variant where applicable,
  3. host-standard-valid,
  4. current-target-deployable.

Do not assume that every recognized variant is deployable on ESP32-P4.

Dataset rules

IEC 61869-9 profile compilation must fail closed when:

  • a channel is not a supported AmpSv/VolSv measurement semantic;
  • every AmpSv.instMag.i is not followed immediately by its corresponding AmpSv.q;
  • every VolSv.instMag.i is not followed immediately by its corresponding VolSv.q;
  • any voltage pair appears before a current pair;
  • current/voltage quantity counts do not match the selected FfSsIiUu variant;
  • order or type cannot be resolved;
  • scale/semantic cannot be determined without guessing.

Do not encode ABB/Siemens/Hitachi channel-count limits into the generic validator.

Device boundary

Current ESP32-P4 remains a separate capability gate.

P1.2 by itself does not authorize:

  • multi-ASDU realtime publication;
  • arbitrary channel count;
  • F4800S2/F14400S6 on hardware;
  • 96 kHz publication;
  • IEC 61869-9 product conformance.

Those require explicit device compilation + runtime/evidence milestones.

AMD1 / future seam

Provide a non-authoritative capability seam for future SynchSrcID / slew-sync semantics if useful, but mark it draft/future. Do not make draft AMD1 behavior mandatory for the published IEC 61869-9 family.

Regression matrix

Require deterministic host tests for:

  • Current scale 1 mA/count;
  • Voltage scale 10 mV/count;
  • valid AmpSv/value+q and VolSv/value+q pairs;
  • wrong ordering / missing Quality / unsupported leaves fail closed;
  • recognized standard variants;
  • preferred F4800S2 and F14400S6 classification;
  • FfSsIiUu quantity-count matching and current-before-voltage ordering;
  • standard-valid but ESP-unsupported distinction;
  • no vendor-specific branch or product-name inference;
  • schema/CLI/Studio evidence exposes semantic + scale without duplicating authority.

Non-goals

No multi-stream scheduler, no PRP/HSR, no automatic relay-vendor compatibility hacks, no hardware conformance claim, no draft AMD1 conformance claim.

Dependency / merge discipline

Activity

  1. self-assigned this
    on Oct 6, 2026
  2. masarray commented on Oct 6, 2026

    @masarray
    OwnerAuthor

    #143 is merged. P1.2 is now the active SMV standards node.

    Exact base: main@9755b5771a9c59e6ed8ef985553dedd39f5ec779
    Working branch: hardening/smv-p1-2-iec61869-profile

    Start from the standards-owned host semantic model only:

    1. exact rational engineering-scale primitive;
    2. explicit IEC 61869-9 FfSsIiUu variant authority;
    3. ordered AmpSv/VolSv + Quality dataset validation;
    4. profile compiler integration and host regression matrix;
    5. CLI/Studio evidence surface consuming the same authority.

    Do not expand the ESP realtime runtime in this node. Standard-valid versus current-device-deployable remains separate.

  3. masarray commented on Oct 6, 2026

    @masarray
    OwnerAuthor

    P1.2 implementation checkpoint

    PR: #145
    Exact base: 9755b5771a9c59e6ed8ef985553dedd39f5ec779
    Exact current head: b19d2e0fc49e167a7da502b9f8cac202060158cc

    Implemented:

    • exact rational IEC 61869-9 current/voltage scale authority;
    • recognized backward-compatible and preferred F/S families;
    • FfSsIiUu identity;
    • canonical AmpSv/VolSv + corresponding Quality validation;
    • FC=MX / CDC=SAV / INT32 measurement gates;
    • current-before-voltage ordering;
    • vendor-neutral I4U4, I3U3 and I1U0 regressions;
    • published-2016 vs draft/future SynchSrcID claim boundary;
    • CLI schema v4 semantic evidence;
    • Studio read-only variant/scaling evidence;
    • legacy GUI consumes compiled 61869 scale instead of owning it;
    • current ESP32-P4 remains explicitly unsupported for IEC 61869-9;
    • CI architecture locks and North Star updated.

    Do not start a parallel P1.2 implementation. Continue only exact-head CI/review fixes on #145.

  4. masarray commented on Oct 6, 2026

    @masarray
    OwnerAuthor

    CI review update

    Exact P1.2 head is now e0066cc6abe5959e4961598c52596438065d097f.

    The earlier SMV Injector GUI failure was a test-contract bug, not an IEC 61869-9 resolver bug:

    • the inspector intentionally returns success after inspecting a document;
    • a rejected stream is represented as compatibilityClass=C, profile=null, with explicit errors;
    • CI incorrectly required the whole inspector process to exit nonzero.

    The workflow now asserts the stream-level JSON contract instead. No protocol/compiler semantics were weakened.

  5. masarray commented on Oct 6, 2026

    @masarray
    OwnerAuthor

    P1.2 exact head advanced to b0b1b00f955bdd9d086155bac3d9aa12d725e9d1. The prior C++/sanitizer failure was a regression-test include boundary only (classify_esp32p4_sv_profile / Esp32P4SvProfileSupport undeclared); the test now includes esp32p4_profile_support.hpp directly. Linux GCC/Clang build + tests and the IEC 61869-9 GUI authority regression have passed beyond the previous failure point. Merge remains blocked on complete exact-head CI.

  6. masarray commented on Oct 7, 2026

    @masarray
    OwnerAuthor

    P1.2 exact head is now af31a8bcefd1018861e4de33d5d87054f7912d74. Review hardening since the initial implementation: (1) direct ESP capability header include fixes the multi-compiler CI boundary; (2) IEC 62351-6-secured IEC 61869-9 input is no longer mislabeled invalid IEC—base semantics stay inspectable/incomplete and deployment remains blocked; (3) full F96000S1 compiler regression proves the 9600 SmpPerPeriod encoding context while deliberately leaving the generic uint16 counter modulus unresolved. Do not merge based on earlier green/failed heads.

  7. masarray commented on Oct 7, 2026

    @masarray
    OwnerAuthor

    P1.2 accepted: PR #145 merged at 0a08767df0352b0311fdcf5d31a9782ccba1a13b after 13/13 exact-head workflows passed. The IEC 61869-9 host variant, ordered AmpSv/VolSv + Quality dataset validation, exact rational engineering scaling, compiler evidence, and Studio/CLI surfaces are merged. ESP32-P4 IEC 61869-9 deployment remains explicitly unsupported pending device/runtime evidence; this was out of scope for #144.

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