# RTL Mini Projects - Memory & Architecture Foundations
This repository contains a collection of RTL mini projects focusing on memory architectures, data movement, buffering techniques, and cache organization commonly used in digital systems and front-end VLSI design.
-> This repository represents Phase-2 Cycle-2: RTL Memory & Architecture Foundations of my RTL learning journey, focused on implementing and verifying fundamental memory subsystems and architectural building blocks using synthesizable RTL design.
The goal of this repository is to:
- Understand memory architecture fundamentals
- Implement memory and controller-based RTL designs
- Learn pointer-based buffering and address management
- Develop self-checking testbenches for verification
- Build a memory-focused RTL portfolio for front-end VLSI roles
## Repository Structure
RTL-Memory-Architecture-Foundations/
├── Week-5/ # Dual-Port RAM
├── Week-6/ # Asynchronous FIFO
├── Week-7/ # DMA Controller
├── Week-8/ # Direct-Mapped Cache Controller
└── README.md
Each folder contains:
- RTL source files
- Testbench
- A dedicated README explaining the design
## Project Overview
| Week | Project | Key Concepts |
|---|---|---|
| 5 | Dual-Port RAM | Synchronous write, asynchronous read |
| 6 | Asynchronous FIFO | Dual-clock buffering, wrap-bit pointers |
| 7 | DMA Controller | Address management, transfer counting |
| 8 | Direct-Mapped Cache Controller | Tag comparison, cache replacement |
## Tools & Skills
- Verilog HDL
- RTL Design
- Memory Architecture Design
- Dual-Port RAM
- Asynchronous FIFO
- DMA Controller
- Cache Memory
- Self-Checking Verification
- HDL Simulation (ModelSim)
- Git
## Learning Outcomes
- Implemented parameterized memory architectures
- Learned pointer-based buffering and FIFO management
- Designed FSM-based DMA control logic
- Applied address decoding and cache organization techniques
- Implemented cache hit/miss detection and cache line replacement
- Developed self-checking testbenches for memory subsystem verification
- Strengthened RTL coding, simulation, and architectural design understanding
# Author: MARK JUSTIN