RISC-V CNN Accelerator Optimization

RISC-V assembly optimization of four address-generation and data-movement kernels for a tiled CNN accelerator. The work targets the transfer path between DRAM, SRAM, and processing-element memory while preserving functional correctness across 168 layer and tiling cases.

Result

Stage	Main change	T	Improvement vs. previous
A	Direct C-to-assembly translation	12.2833	baseline
B	Four-word block copies	7.8545	1.56x
C	1x1 rAGU fast path	4.8600	1.62x
D	Layer-1 3x3x4 micro-kernel	4.0068	1.21x
E	Layer-specific rAGU and wAGU paths	3.2571	1.23x
Final	Controlled rDMA and wDMA unrolling	3.1217	1.04x

The cumulative improvement from the first direct assembly version to the final implementation is 3.93x, with a reported final cost of 46.8M. T and cost are simulator-specific project metrics rather than physical hardware throughput.

Kernel responsibilities

flowchart LR
    DRAM_IN["DRAM input"] -->|ag_rDMA| SRAM_IN["Input SRAM tile"]
    SRAM_IN -->|ag_rAGU| PE_IN["PE input window"]
    PE_OUT["PE output"] -->|ag_wAGU| SRAM_OUT["Output SRAM tile"]
    SRAM_OUT -->|ag_wDMA| DRAM_OUT["DRAM output"]

Loading

• ag_rDMA: copies an input tile, including the convolution halo, from DRAM to SRAM.
• ag_rAGU: extracts each receptive field from SRAM and places it in PE input memory.
• ag_wAGU: stores PE output channels into the output SRAM tile.
• ag_wDMA: writes the completed output tile from SRAM back to DRAM.

Optimization strategy

• Prioritize per-pixel rAGU and wAGU paths because they execute more frequently than per-tile DMA paths.
• Replace scalar copies with four-word load/store groups to reduce loop and branch overhead.
• Detect 1x1 convolution layers and remove unnecessary spatial loops.
• Use fixed-shape micro-kernels for repeated 3x3 layer configurations.
• Dispatch by layer shape and channel count, keeping common paths close to fall-through.
• Fully unroll only selected DMA tile cases where measured benefit justifies code size.
• Generate the largest assembly files from deterministic Python scripts to keep unrolled schedules reproducible.

Repository layout

.
|-- docs/         Optimization and reproducibility notes
|-- generators/   Python generators for the submitted assembly
|-- results/      Complete 168-case tiling sweep
`-- src/          Final C harness and four assembly kernels

All source, generator, and result files are copied unchanged from the final project workspace. The report, slides, score sheets, course material, simulator binaries, intermediate versions, and submission archives are not included.

Reproducibility

The three generators reproduce all four final assembly files exactly, apart from the platform-native LF/CRLF line ending:

python generators/generate_dma_final.py
python generators/generate_ragu_final.py
python generators/generate_wagu_final.py

The generated root-level assembly files are ignored by Git. GitHub Actions performs the same regeneration and compares the output after normalizing only CRLF/LF line endings on every push.

Build environment

src/addr_gen.c uses project-specific memory maps, simulator hooks, and register-storage annotations. The repository therefore documents and preserves the optimized kernels but does not provide the proprietary simulator or course testbench required for standalone execution.

See optimization notes and reproducibility notes for more detail.

License

MIT