Pinned Loading

1. RISC_V_PIPELINED_CPU_DESIGN RISC_V_PIPELINED_CPU_DESIGN Public

   **RISC-V Pipelined Processor with Hazard Forwarding:** Designed a 5-stage pipelined RISC-V processor in Verilog with hazard detection, data forwarding, and pipeline stall logic to resolve RAW hazar…

   Verilog

2. axi_protocol_uvm_verification axi_protocol_uvm_verification Public

   Developed a UVM-based verification environment for the AXI protocol, including driver, monitor, sequencer, scoreboard, and functional coverage to verify AXI read/write transactions and protocol com…

   SystemVerilog

3. STM32F407_MCU_DRIVER_DEVELOPMENT STM32F407_MCU_DRIVER_DEVELOPMENT Public

   **STM32F446xx MCU Driver Development (Bare Metal):** Developed reusable bare-metal peripheral drivers for the STM32F407 microcontroller in Embedded C, including GPIO, SPI, I2C, UART, and RCC module…

   C 1

4. FPGA_ZYNQ_OLED_INTERFACING_USING_SPI_CONTROLLER FPGA_ZYNQ_OLED_INTERFACING_USING_SPI_CONTROLLER Public

   This project demonstrates OLED interfacing on the Zynq FPGA by utilizing both the Processing System (PS) and Programmable Logic (PL). The PS generates and sends customized messages through the SPI …

   Verilog 1

5. linux_device_driver linux_device_driver Public

   Collection of Linux kernel modules and device drivers demonstrating character drivers, GPIO interfacing, kernel APIs, synchronization mechanisms, and driver development concepts on embedded Linux s…

   C 1

6. PCB_DESIGN_TI28027-VI-Measurement-Card_CADENCE_Tools PCB_DESIGN_TI28027-VI-Measurement-Card_CADENCE_Tools Public

   Four-layer PCB design of a TI28027 microcontroller based Voltage and Current (V&I) Measurement Card using Cadence OrCAD Capture CIS and Allegro PCB Designer.

   Alloy