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seven-segment-display

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15-bit number magnitude comparator with 7-segment display with class-provided testbenches

circuit comparator segmented-displays seven-segments-display systemverilog verilog

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Name		Name	Last commit message	Last commit date
README.md		README.md
bcd7seg.sv		bcd7seg.sv
bcd7seg_tb.sv		bcd7seg_tb.sv
cmp1bit.sv		cmp1bit.sv
cmp1bit_tb.sv		cmp1bit_tb.sv
mag15.sv		mag15.sv
mag15_tb.sv		mag15_tb.sv
segAdec.sv		segAdec.sv
segBdec.sv		segBdec.sv
segCdec.sv		segCdec.sv
segDdec.sv		segDdec.sv
segEdec.sv		segEdec.sv
segFdec.sv		segFdec.sv
segGdec.sv		segGdec.sv

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15-bit Number Comparator on 7-Segment Display

Digital Systems class project, implemented for use on an FPGA

About

15-bit number magnitude comparator with 7-segment display with class-provided testbenches

circuit comparator segmented-displays seven-segments-display systemverilog verilog

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