Architect and researcher specializing in high-performance storage, hardware-software co-design, and modern AI-Driven Software Development. I design robust system architectures, specify interfaces, and leverage advanced generative models to accelerate implementation, testing, and delivery cycles.

• Languages: Rust, C++11, C (Bare-Metal / Firmware), Python.
• Storage & Systems Engineering: NVMe ZNS (Zone Namespaces), Open-Channel SSD 2.0, FTL, io_uring, POSIX O_DIRECT, SPDK.
• Hardware Co-Design & ПЛИС: Verilog, LiteX SoC Framework, Migen, Xilinx Vivado (Artix-7), Verilator.
• Infrastructure & Data Plane: NixOS (Flakes), Kubernetes, mTLS, Kafka, ClickHouse.
• AI-Guided Workflow: Cursor, GitHub Copilot, custom LLM pipelines for RTL-generation and automated testing.

• Concept: A high-fidelity research environment (Golden Model) for validating custom FTL algorithms and NVMe ZNS standards.
• Architecture: Fully isolated User-Space execution bypassing Linux kernel noise. Features a hybrid Co-Simulation engine utilizing Verilator to bind a functional C++ model with synthesizable Verilog state machines (zns_fsm_validator.v) over network sockets.
• AI Integration: Used LLMs to build dynamic combinatorial zone-resolvers without division operators and auto-generated multi-threaded integration stress-tests in Rust.

• Concept: Distributed lock-free in-memory calculation complex processing trillion-scale Riemann Zeta function non-trivial zeros (t ~ 10¹²) to correlate them with Gaussian Unitary Ensemble (GUE) nuclear spectra.
• Performance: Achieved 210+ GB/sec raw binary streaming directly from block devices using io_uring and O_DIRECT. Scaled linearly across 128 cores via NUMA-friendly thread isolation.

• Concept: Automated System-on-Chip (SoC) generator wrapping custom hardware validators into Wishbone/AXI bus ecosystems for Xilinx Artix-7 FPGA target chips.
• Deliverables: Synthesized configuration registers (CSR map) and created a low-level bare-metal C driver running natively on softcore RISC-V processors inside storage arrays.

• Infrastructure R&D (FPlus): Pioneering next-generation Russian data storage cores, Active-Active HA setups (nbdcache), PMEM WAL journaling, and automated NixOS validation ecosystems.
• Fintech & Core Platforms (UBRR / Sber CIB): Architectural oversight of front-office business scenarios, zero-login zone abstractions, digital onboarding paths, and enterprise DWH system designs.

• History & Linguistics: Passionate about Sanskrit linguistics, chronicles, and mediaeval history.
• Hardware Archaeology: Author of a hardware emulator for the "Dnepr" (the first Soviet semiconductor computer).
• Industrial Heritage: Graduate of the Engineer's Eyes school; certified tour guide ready to reveal the tech secrets of Nizhny Novgorod.

• Telegram: @juhnowski
• Email: juhnowski@gmail.com

• Coursera: "Architecting with Google Kubernetes Engine", "Building Scalable Java Microservices", "Data Visualization" | 2019
• IBM: "Programming a Quantum Computer with Qiskit" | 2020
• СПБ ГУ: Квантовые вычисления (Quantum computing) | 2020
• Google Cloud: "Machine Learning Engineering for Production" | 2021
• University of Maryland, College Park: Cryptography
• DeepLearning.AI: Structuring Machine Learning Projects