GitHub - jievince/NSCSCC2-CPU: 5-stages MIPS CPU

a 139MHZ Mips-5-stages-pipeline-cpu designed in NSCSCC 2.

Name		Name	Last commit message	Last commit date
Latest commit History 6 Commits
.travis.yml		.travis.yml
CP0.v		CP0.v
Dcache.v		Dcache.v
HiLo.v		HiLo.v
Icache.v		Icache.v
Memory_System.v		Memory_System.v
README.md		README.md
RegFile.v		RegFile.v
branch.v		branch.v
dec_stage.v		dec_stage.v
exe_stage.v		exe_stage.v
if_stage.v		if_stage.v
ip.zip		ip.zip
mem_stage.v		mem_stage.v
mycpu_top.v		mycpu_top.v
wb_stage.v		wb_stage.v

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