This repository contains coursework submission for an Imperial College Module on Instruction Architecture. The codebase implements a 32-bit big-endian MIPS architecture CPU, compatible with Avalon Bus Interface. The CPU was written to fit the specifications defined here, scoring 91% on the coursework.
Test benches were written to verify the functionality of the CPU. The testing approach can be summarised in the chart below.
- Derek Lai
- Eng Jian Fu
- Weihan Huang
- Chris Myers
- Luca Chammah
- Ziyad Ansari