This project presents the design and implementation of a simple 4-bit processor using Verilog HDL. The processor follows a basic instruction execution cycle consisting of Fetch, Decode, Execute, and Write-Back stages. The design was developed and simulated using Xilinx Vivado.
The objective of this project is to understand the fundamentals of processor architecture, register file operations, instruction execution, ALU design, and hardware verification through simulation.
The processor is divided into four major stages:
- Maintains the Program Counter (PC)
- Fetches instructions from Instruction Memory
- Updates PC for the next instruction
- Decodes opcode and register fields
- Reads operands from the Register File
- Provides operands to the Execute stage
- Performs arithmetic and logical operations
- Generates status flags
- Produces execution results
- Writes ALU results back to the Register File
- Updates destination registers
| Opcode | Instruction | Description |
|---|---|---|
| 0000 | ADD | Addition |
| 0001 | SUB | Subtraction |
| 0010 | AND | Bitwise AND |
| 0011 | OR | Bitwise OR |
| 0100 | MOV | Move Data |
| 1111 | NOP | No Operation |
The processor contains:
- 4 Registers
- 4-bit Register Width
- Two Read Ports
- One Write Port
- fetch_unit.v
- decode_unit.v
- execute_unit.v
- write_back.v
- top_alu.v
- top_alu_tb.v
- Verilog HDL
- Xilinx Vivado
- Git
- GitHub
The processor was successfully simulated using Vivado Simulator. The waveforms verify:
- Program Counter Operation
- Instruction Fetching
- Instruction Decoding
- ALU Execution
- Register Write-Back
Simulation screenshots are available in the repository.
This project helped in understanding:
- Processor Architecture
- RTL Design Methodology
- Register File Design
- ALU Design
- Verilog HDL Coding
- Functional Verification using Simulation
- Git and GitHub Version Control
Jay Jain