8-bit ALU using Verilog HDL

Overview

This project implements an 8-bit Arithmetic Logic Unit (ALU) using Verilog HDL. The ALU performs arithmetic and logical operations based on a 3-bit opcode.

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Features

• 8-bit Arithmetic and Logical Operations
• Functional Verification using Verilog Testbench
• Simulation using Icarus Verilog
• Version Control using Git and GitHub

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Supported Operations

Opcode	Operation
000	Addition
001	Subtraction
010	AND
011	OR
100	XOR
101	NOT
110	Left Shift
111	Right Shift

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Block Diagram

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Simulation Waveform

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Project Structure

8bit-ALU/
│
├── docs/
├── src/
├── testbench/
├── README.md
└── .gitignore

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Tools Used

• Verilog HDL
• Icarus Verilog
• VS Code
• Git
• GitHub

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How to Compile

iverilog -o alu_sim src/alu.v testbench/alu_tb.v

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How to Run

vvp alu_sim

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Author

Ishita Chaudhary