fbgemm-xpu: port expand_into_jagged_permute to SYCL/XPU - #123
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dvrogozh merged 8 commits intoAug 28, 2026
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Add a SYCL implementation of the FBGEMM expand_into_jagged_permute operator for Intel XPU, mirroring the CUDA kernel structure: - add the 2D nd_range functor and XPU dispatch implementation; - validate that all inputs share one XPU and launch on that device's current stream, preserving correctness in multi-XPU applications; - register the guarded schema and add the kernel to host_sources; - enable expand_into_jagged_permute_test.py for XPU in the FBGEMM test patch. Validated on an Intel B60 with torch 2.13.0+xpu. The standalone patch applies cleanly and its test files pass on XPU (8 passed, 11 skipped for CUDA-only or not-yet-ported cases).
Follow the shared accelerator convention so the patched test exercises the active backend without hardcoding CUDA or XPU.
Pick up the permute_2D_sparse_data split and torchcodec updates from main while retaining both guarded operator schemas. Co-authored-by: Cursor <cursoragent@cursor.com>
Retain the expand_into_jagged_permute implementation while incorporating the upstream block_bucketize operator and TorchCodec documentation update. Combine the FBGEMM test patch and keep the host source list alphabetically ordered.
dvrogozh
requested changes
Aug 25, 2026
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|
Rebase, please as other patch we merged gives a conflict. |
aagalleg
reviewed
Aug 25, 2026
aagalleg
reviewed
Aug 25, 2026
Contributor
|
Also, please, update README following #124. |
Retain the expand_into_jagged_permute schema, kernel, and test enablement while picking up the get_infos_metadata XPU dispatch, the README supported- operator list, and the TBE utils CI entries from main. Keep the CMake host_sources list alphabetically ordered and regenerate the FBGEMM test patch so both test additions land in one patch.
Template ExpandIntoJaggedPermuteKernel on <index_t, offsets_t> and type the offset pointers as offsets_t, mirroring the CUDA kernel so the index and offset roles stay distinguishable. Swap the two nd_range dimensions. SYCL varies the last dimension of an nd_item fastest, whereas CUDA varies threadIdx.x fastest, so the previous 1:1 transcription mapped consecutive work-items onto different tables and scattered the stores to output_permute. Mapping CUDA .x onto SYCL dimension 1 restores coalesced stores: 4096x4096 elements go from 0.886 ms to 0.343 ms (303 -> 782 GB/s) on an Intel B60.
The test-fbgemm job enumerates pytest modules explicitly, so the test enabled by the FBGEMM patch would otherwise never run.
It is part of the documented FBGEMM sparse ops stable API, so it belongs in the first list introduced by intel#124.
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Summary
Port
fbgemm::expand_into_jagged_permuteto SYCL/XPU by mirroring the existing CUDA two-dimensional launch structure and grid-stride algorithm.Changes
ExpandIntoJaggedPermuteKernel<index_t>SYCL functor.expand_into_jagged_permute_xpuhost launcher.int32andint64index tensors.TORCH_LIBRARY_IMPL(fbgemm, XPU, m).ops_registry.cpp.host_sources.host_sourceslist alphabetically ordered.accelerator_available;current_accelerator();.to(device).Kernel mapping
The SYCL work-group mirrors the CUDA launch:
For every output segment:
Upstream synchronization
The merge:
expand_into_jagged_permuteschema and XPU implementation;host_sourceslist alphabetically ordered.Validation
Validated with:
2.13.0+xpuv1.8.0Results:
torch.xpu.is_available() == Trueimport fbgemm_xpusucceedsint32andint64paths passThe skipped tests require CUDA or operators that have not yet been ported to XPU.
CC: @dvrogozh @flezaalv @aagalleg