Collapse adjacent bit selects in swizzles to ranges#674
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desmonddak
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Jul 1, 2026
desmonddak
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Jul 1, 2026
| operands.add((expression: expression, width: input.width)); | ||
| } else { | ||
| operands.add(( | ||
| expression: '${selectedBit.source}[${selectedBit.index}:$lowerIndex]', |
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IT would be kinda fun to add the SV shorthands for when you are selecting up to the end of the array, or reverse-indexing.
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are those safe with all tools? generally have been trying to keep things minimal fanciness to maximize tool compatibility
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I think this PR makes sense right now to get SV much cleaner. I could see pushing some of the optimizations into the base and leaving here some SV-specific conventions like [:7]. Otherwise, the collapse could be structural, and then the strings would come out from there unless we are avoiding structural change in the synth layer for this case. |
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Description & Motivation
This improves generated SystemVerilog for swizzles by compacting descending contiguous single-bit selections into legal slice expressions.
Examples:
{a[7], a[6], a[5]}can now emit asa[7:5]{arr[0][1], arr[0][0]}can now emit asarr[0][1:0]The collapse is intentionally conservative. It only applies to descending contiguous bit selects from the same packed source, and leaves unsupported cases expanded, including ascending selections, adjacent pre-existing range operands, expression-based selects, nested swizzle boundaries, and unpacked array sources.
Related Issue(s)
N/A
Testing
Added new tests, updated some other tests
Backwards-compatibility
No
Documentation
No