Element, subset, and swizzle collapsing in generated SV#663
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| SimCompare.checkIverilogVector(mod, vectors); | ||
| }); | ||
| } | ||
| }); |
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I didn't see any naming checks to see if you end up retaining only basename nets or accidentally toss that net and keep one with _0. I think this code is not enforcing the namig order, but it would be good to have a test for it and know how you are going to enforce better names (with a current test that you waive).
| await SimCompare.checkFunctionalVector(mod, vectors); | ||
| SimCompare.checkIverilogVector(mod, vectors); | ||
| }); | ||
| } |
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I test is needed where a SynthLogic has been merged before a specific aggregate collapse happens.
element <= intermediate;
intermediate <= realSource;
You want to be sure you don't see the intermediate kept.
| // --- functional correctness (always) --- | ||
| await SimCompare.checkFunctionalVector(mod, vectors); | ||
| SimCompare.checkIverilogVector(mod, vectors); | ||
| }); |
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Need a test showing a partial assignement is not collapsed.
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I think it makes sense to commit this PR for cleaning up the major cases. Two main arch points to prepare for is the naming problem, which we tried to solve in central_naming by marking first in the synth base classes, and then another is to think about what will be common optimizations versus SV specific. Unfortunately a netlist branch is not yet in and that has a really general approach to deal with nested assignments and series of pack/unpack/pack as well as subset/concat/subset which can occur in a nested fashion (a very wide interface split into subsets and then recombined in a couple levels possibly with some splits and recombines and finally end up at the very same interface. Then mixed array and struct assignments, reversals, etc. all get very tricky, especially with partial assignments and subset assignments. Worth thinking about a general optimization approach along with the naming issue. Nested Interface assignments containing busses is the source of these. |
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Description & Motivation
This PR dramatically improves SV generation by reducing the amount of unnecessary assignments,
net_connects, swizzles, subsets, and intermediate signals forLogics andLogicArrays (both net and non-net) in generated SystemVerilog. This makes the SV much more readable, debuggable, and tool friendly.Related Issue(s)
N/A
Testing
Added extensive new testing for collapsing capabilities, existing suite helps protect.
Backwards-compatibility
No
Documentation
No