Central synthesizer naming#652
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mkorbel1
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I haven't finished reading it all yet, but first pass a few questions
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This is looking pretty good, thank you for refactoring it this way, I can see how it helps your other upcoming changes!
…al/instance naming routine names
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Looking close now to mergeable!
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Two new tests in 'shared instance and signal namespace': 1. 'instance name wins the shared namespace; signal gets the suffix' Asserts deterministic ordering: non-reserved instances are picked before non-reserved signals, so the instance keeps the bare name and the colliding signal is uniquified to inner_0. 2. 'instance-signal collision resolution is stable across repeated synthesis passes' Calls generateSynth() twice and verifies the module body is identical (timestamp stripped). Guards against name drift where the second pass would assign different suffixes.
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I use Resolve if I think I have fixed. I accidentally thought I had resolved one I had not in the last round. But otherwise, you may not know I have read and attempted a fix. |
Add regression test for _BusSubsetForStructSlice.instanceNameKey.
Each SynthModuleDefinition pass creates fresh _BusSubsetForStructSlice
instances for any submodule with a LogicStructure output port. Without
the instanceNameKey override those instances use 'this' as the cache key,
so the namer allocates a new suffix every pass ('struct_slice' → 'struct_slice_0').
Restoring _destination and overriding instanceNameKey => _destination pins
the cache to the stable destination Logic, keeping names consistent.
Fixes: _BusSubsetForStructSlice._destination removed in 249b210.
Records which Logic the namer chose as the source of each signal name (an additive reverse map; does not influence naming). Lets source-trace and cross-probe callers attribute a merged net to its declared signal rather than an arbitrary internal signal that merged into the same net.
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some feedback not addressed, and also new weird thing added?
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Description & Motivation
Migrate synthesis naming to a central namer so that all synthesizers (and even WaveDumper) can agree on signal naming.
This is needed for a new synthesizer to be added (netlist).
Related Issue(s)
None.
Testing
I ran existing examples in ROHD and compared SV.
I added extensive test matrix
test/naming_cases_test.dartfor the combinations of naming options (reserved, mergeable, etc) for which I generated tests that pass before and after the central naming.Two bugs were filed: bug #648 and bug #649 which are fixed in PR # 650 for the traditional SV code as well as in this PR for central naming).
I ran a very, very, very large design example and compared SV before and after.
Backwards-compatibility
Naming is slightly different due to ordering, so when we do have collisions, we will see _0, _1 on different signals. Plus the two bug fixes involving unnamed substructures and repeated const names.
Documentation
No. None needed.