8-Bit Processor Architecture & Simulation (SAP-1 Based)

This project is a custom 8-bit processor architecture built from scratch to demonstrate the fundamental working principles of modern computer architectures. All hardware components, data buses, and control units of the design have been implemented and functionally verified within the Logisim-Evolution simulation environment.

Developed as a term project for the BLG210 – Computer Architecture and Organization course at Istanbul Rumeli University, Faculty of Engineering and Natural Sciences, Department of Computer Engineering.

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Key Features

• Fully Visual and Functional Hardware: A complete, runnable processor schematic on Logisim-Evolution.
• 6 Different Operations Support: Multiplexer (MUX)-based operation selection within the ALU (ADD, SUB, MUL, DIV, AND, OR).
• Two's Complement Arithmetic: Hardware representation and processing of negative numbers.
• Real-Time Output Tracking: An integrated 7-segment display structure connected to the Accumulator (ACC) output.

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Processor Components

1. Registers: 8-bit D-Type Flip-Flop based Register A and Register B that temporarily store operands.
2. Instruction Register (IR): A special-purpose register holding the opcode field coming from RAM or the user.
3. Accumulator (ACC): The central register where ALU results are written and which provides direct data to the display screen.
4. Arithmetic Logic Unit (ALU): The computational core. A MUX architecture that generates data according to a 2-bit selector (Sel) signal.
5. RAM Memory: A 16×8-bit memory block that stores initial data values and instructions.
6. Control Unit & Decoder: The processor management center that decodes opcode bits and activates the corresponding data buses.

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Instruction Set

IR[2:0] Bits	Mnemonic	Hex Code	Description
000	ADD	0x00	Add Register A and B, write result to ACC
001	SUB	0x01	Subtract Register B from A, write result to ACC
010	MUL	0x02	Multiply Register A and B, write result to ACC (truncated to 8-bit)
011	DIV	0x03	Divide Register A by B, write integer quotient to ACC
100	AND	0x04	Perform bitwise AND between A and B
101	OR	0x05	Perform bitwise OR between A and B

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Simulation and Test Environment

To test the system, Register A = 0x05 (5) and Register B = 0x03 (3) values have been loaded into the RAM by default. The verified results read from the Display screen upon executing the instructions are as follows:

• ADD: 5 + 3 = 8 ($\rightarrow$ 08h on screen)
• SUB: 5 - 3 = 2 ($\rightarrow$ 02h on screen)
• MUL: 5 × 3 = 15 ($\rightarrow$ 0Fh on screen)
• DIV: 5 ÷ 3 = 1 ($\rightarrow$ 01h on screen - Integer Quotient)
• AND: 0101 AND 0011 = 0001 ($\rightarrow$ 01h on screen)
• OR: 0101 OR 0011 = 0111 ($\rightarrow$ 07h on screen)

Technical Note: The bit-width mismatch problem between the 1-bit individual outputs of the Decoder and the ALU MUX during the design process was resolved using a Splitter circuit that merges 1-bit signals into a 2-bit Sel bus structure.

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Running the Project

1. Download the Logisim-Evolution simulator to your computer.
2. Clone this repository: git clone https://github.com/your-username/8-Bit-Processor-Simulation.git
3. Open the Logisim-Evolution application and include the src/main.circ file into the project by following File -> Open.
4. You can start the clock signal cycle by enabling the Simulate -> Auto-Tick Enabled option.

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Developer

• Name Surname: İlayda Meryem Coşkun
• Student ID: 241201019
• Institution: Istanbul Rumeli University - Department of Computer Engineering

License

This project is licensed under the MIT License.