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perf: publish U5 FPGA loopback throughput evidence - #15

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ichigo-6301 wants to merge 2 commits into
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perf/dma-u5-fpga-emulation-evidence
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ichigo-6301 wants to merge 2 commits into
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perf/dma-u5-fpga-emulation-evidence

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@ichigo-6301

@ichigo-6301 ichigo-6301 commented Aug 17, 2026

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Summary

  • publish one bounded XC7Z100 synchronous PL-loopback board observation
  • preserve the exact operator-transcribed debugger fields and recompute all rates with Python Decimal
  • publish the SDK source only as a reproduction reference, not as retained source-to-binary build provenance
  • register a partial, public, non-resume-eligible FPGA Claim under the base-owned policy merged through PR policy: tighten FPGA evidence publication boundaries #16
  • leave RTL, profiles, ASIC Evidence, Async64 simulation Evidence, and frozen release content unchanged

Observation

  • profile: 13 RX / 13 TX, TX0 to RX0, synchronous 512-bit PL-local loopback
  • memory boundary: existing 64-bit HP0 at 100 MHz
  • workload: 1024 x 4096-byte frames
  • payload: 4,194,304 bytes
  • timer: 8,969,535 XTime ticks at COUNTS_PER_SECOND=333333343
  • rounded equivalent PL cycles: 2,690,860
  • post-start-write-return completion-window rate: 1.558722 MB/s/MHz
  • at 100 MHz: 155.872225 MB/s / 1.246978 Gb/s
  • relative to the conservative 4 B/cycle shared-HP0 model: 38.968056%

Evidence Boundary

Classification: FPGA_DEBUGGER_TRANSCRIBED_SINGLE_RUN.

The raw debugger fields were transcribed after the timing and correctness gates. No independent screenshot, debugger session export, or memory dump was retained. The public helloworld.c is a fixed source-only reproduction reference; the retained private ELF and bitstream are identified by size and SHA-256, but no retained build manifest cryptographically links those binaries to the public source.

The timer starts after the descriptor-start register write returns. The metric is therefore a post-start-write-return completion-window payload rate, not launch-to-completion hardware end-to-end throughput.

Review Fixes

  • add and hash debugger_capture_transcript.txt
  • downgrade capture wording from debugger-captured to operator-transcribed
  • remove the unretained source-to-ELF/bitstream build-chain assertion
  • compute model efficiency from the unrounded tick rational
  • authorize only the fixed source-only fpga/u5/benchmark exception
  • rename and bind the measured timing window honestly

Validation

  • local/WSL make showcase-check: 337 tests passed, 1 expected skip
  • FPGA_EMULATION_EVIDENCE_PASS
  • browser render: 6 assets, 256 text nodes, 37 regions, 4 homepage cases
  • public hygiene: 346 checksums, 14 README claims, 8 showcase assets
  • ASIC Evidence and Async64 publication gates: pass
  • frozen v0.1.0-rc1: unchanged and pass
  • checksum and git diff --check: pass
  • final GitHub tree equals locally validated tree 7d20a9e996d246dcff43a0397308991f02431a86

Nonclaims

  • automated UART capture: no
  • repeated-run statistics: no
  • steady-state first-frame-excluded result: no
  • Async64 CDC board test: no
  • Aurora performance: no
  • DDR peak or FPGA Fmax: no
  • 64 B/cycle Writer result: no
  • ASIC result: no
  • resume eligible: no

Scope

  • production RTL changed: no
  • profile/config/filelist/constraint changed: no
  • existing ASIC/Async64 Claim numeric changed: no
  • release tag changed: no
  • PR merged: no

Publish one debugger-captured 1024-frame U5 loopback observation with fixed source, artifact, counter, and claim boundaries.

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@codex review

Please review the bounded U5 FPGA evidence publication at 8dbaf7672e8453a664ae5aa35e5dfeac62f37faa. Focus on counter derivation, artifact/source binding, claim boundaries, sensitive-data hygiene, and base-owned scope enforcement.

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💡 Codex Review

Here are some automated review suggestions for this pull request.

Reviewed commit: 8dbaf7672e

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Comment thread evidence/fpga_emulation/u5_sync_hp0_loopback/raw_counters.csv Outdated
Comment thread evidence/fpga_emulation/u5_sync_hp0_loopback/artifacts.csv Outdated
Comment thread evidence/fpga_emulation/u5_sync_hp0_loopback/derived_metrics.csv Outdated
Comment thread fpga/u5/benchmark/README.md Outdated
Comment thread fpga/u5/benchmark/helloworld.c
Merge the reviewed base-owned policy from main and correct PR #15 to publish only an operator-transcribed single-run observation with a post-start-write-return completion window.

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@codex review

Please review corrected head 60c9af361717bf6f95e253e6451c98e21ddb5f92 against merged base policy 8a0ac6be0482ddce84fd4e56a0bb51fbc7917b19. Focus on the operator-transcribed single-run classification, absence of retained source-to-binary build provenance, direct unrounded Decimal efficiency derivation, exact source-only public-scope exception, and the post-start-write-return timing boundary.

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Codex Review: Didn't find any major issues. 🚀

Reviewed commit: 60c9af3617

ℹ️ About Codex in GitHub

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  • Open a pull request for review
  • Mark a draft as ready
  • Comment "@codex review".

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Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".

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