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relokin
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Overall looks good to me but I have a couple of comments about the tests.
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Hi @relokin. What this PR basically does is changing the test that controls performing the store conditional. First observe that the reservation (a.k.a exclusive monitor) is implemented by using a unique register RES (for AArch64, VMSA and ASL. VMSA+ASL uses an additional flag). Schematic behaviour is a follows
See also the tests L020 (LDXR and STXR to different addresses, store was always failing now it may succeed) and L021 (LDXR followed by two STXR, all to the same address, the second STXR never succeeds). Finally an new test L106 consists in a simple STXR, without LDXR, the store normally always fails but may succeed when |
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I have also added L107 (L021 with |
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Looks good to me. Perhaps one concern I have is that for AArch64 |
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Hi @relokin and @HadrienRenaud. Rebased on master since prerequisite PR #1889 is merged, all commits squashed into two commits, ready for review. |
HadrienRenaud
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This looks ok to me but I think the handling of reserved addresses in ASL could be cleaner.
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Not really the point of this PR so you can go ahead and merge as soon as @HadrienRenaud is happy but I don't understand why we support |
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I do not understand the intent of |
My bad, this usage is for generators... Hence we can suppress |
The purpose of this variant was unclear. In practice it was permitting issuing invalid behaviours architecturally speaking. (see #1896 (comment)) We this supressit it as a prelude to PR #1896.
The purpose of this variant was unclear. In practice it was permitting issuing invalid behaviours architecturally speaking. (see #1896 (comment)) We this supressit it as a prelude to PR #1896.
The purpose of this variant was unclear. In practice it was permitting issuing invalid behaviours architecturally speaking. (see #1896 (comment)) We thus supress it as a prelude to PR #1896.
Given x and y that are different addresses `LDXR x; ...; STXR y`, STXR to y can succeed. Hence, the only situation when STXR always fail is when there is no reservation, which we implement by the reservation address being null. Detailed changes: + The new semantics is also implemented for AArch64 ASL and ASL+VMSA modes + With `-variant ConstrainedUnpredictable`, STXR can succeed even in the absence of a reservation (non-ASL only, no access to variant in ASL). + Same semantics of LR/SC pairs for RISCV Notice that this semantics (SC can succeed event with a reservation to a different address) was activated by the variant `LrScDiffOk`. This behaviour now being the default, we suppress the variant.
+ Add constrained unpredictable tests Note that these tests are disabled in ASL mode. (No access to the ConstrainedUnpredicable variant) + Add "LDXR x; LDXR y, STXR x" tests.
| ASLS.A.state_add st (ASLS.A.Location_reg (ii.A.proc, loc)) v | ||
| in | ||
| let add_reg_if_present reg loc st = | ||
| let add_reg_if_present ?(setzero=false) reg loc st = |
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I believe this is not necessary anymore? I don't think add_reg_if_present is called with setzero?
The following test may succeed on hardware and is legal.
Have herd7 to perform store-exclusive even when the reserved address is different. In practive we encode the absence of a reservation with the ResAddr (or
RES) register holding zero. Hence the store exclusive may succeeed whenever ResAddr does not hold zero. Further notice that executing a store exclusive instruction voids the reservation, regardless of the write being performed or not.