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Resolve conflict: keep THEIRS for ad_iobuf.v #18

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Resolve conflict: keep THEIRS for ad_iobuf.v #18

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166 changes: 0 additions & 166 deletions library/axi_tdd/axi_tdd_channel.sv
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33 changes: 32 additions & 1 deletion library/axi_tdd/axi_tdd_counter.sv
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -55,6 +55,37 @@ module axi_tdd_counter #(
output logic tdd_endof_frame
);

typedef enum logic [1:0] {
IDLE = 2'b00,
ARMED = 2'b01,
WAITING = 2'b10,
RUNNING = 2'b11
} state_t;
//jkh

typedef enum logic [1:0] {
IDLE = 2'b00,
ARMED = 2'b01,
WAITING = 2'b10,
RUNNING = 2'b11
} state_t;

typedef enum logic [1:0] {
IDLE = 2'b00,
ARMED = 2'b01,
WAITING = 2'b10,
RUNNING = 2'b11
} state_t;
//gttt

typedef enum logic [1:0] {
IDLE = 2'b00,
ARMED = 2'b01,
WAITING = 2'b10,
RUNNING = 2'b11
} state_t;
//gttt

// package import
import axi_tdd_pkg::*;

Expand Down
11 changes: 8 additions & 3 deletions library/axi_tdd/axi_tdd_pkg.sv
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2022-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2022-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down Expand Up @@ -39,11 +39,16 @@ package axi_tdd_pkg;
IDLE = 2'b00,
ARMED = 2'b01,
WAITING = 2'b10,
RUNNING = 2'b11} state_t;
RUNNING = 2'b11
} state_t;

localparam
PCORE_VERSION = 32'h00020062,
PCORE_MAGIC = 32'h5444444E; // "TDDN", big endian
PCORE_MAGIC = 32'h5444444E; //"TDDN", big endian

localparam
PCORE_VERSION = 32'h00020062,
PCORE_MAGIC = 32'h5444444E; //"TDDN", big endian

// register address offset
localparam
Expand Down
2 changes: 1 addition & 1 deletion library/common/ad_iobuf.v
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Original file line number Diff line number Diff line change
Expand Up @@ -41,7 +41,7 @@ module ad_iobuf #(
) (
input [(DATA_WIDTH-1):0] dio_t,
input [(DATA_WIDTH-1):0] dio_i,
output [(DATA_WIDTH-1):0] dio_o,
output [(DATA_WIDTH-1):0] d
inout [(DATA_WIDTH-1):0] dio_p
);

Expand Down
2 changes: 1 addition & 1 deletion projects/adrv9009/zcu102/system_top.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2024 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down
2 changes: 1 addition & 1 deletion projects/daq2/zc706/system_top.v
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Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
// ***************************************************************************
// ***************************************************************************
// Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
// Copyright (C) 2014-2025 Analog Devices, Inc. All rights reserved.
//
// In this HDL repository, there are many different and unique modules, consisting
// of various HDL (Verilog or VHDL) components. The individual modules are
Expand Down
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