GitHub - franciszekjuras/firIP: Implementation of FIR filter with time multiplexing and upsampling in Verilog. · GitHub

Name		Name	Last commit message	Last commit date
firIP_1.0		firIP_1.0
.gitignore		.gitignore
coefs.dat		coefs.dat
data.dat		data.dat
dwsamp_coefs.dat		dwsamp_coefs.dat
edit_firIP_v1_0.xpr		edit_firIP_v1_0.xpr
fir_tb_behav_internal_connections.wcfg		fir_tb_behav_internal_connections.wcfg
fir_tester.nb		fir_tester.nb
upsamp_coefs.dat		upsamp_coefs.dat

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Implementation of FIR filter with time multiplexing and upsampling in Verilog.

dsp finite-impulse-response fir time-multiplexing upsampling verilog

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