arcv: CRC32 for RV32 using clmulr - #311
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https://lkml.org/lkml/2024/6/21/204 the linux kernel also has this in assembly performance goes from +- 17 cycles/byte to +- 1 cycle per byte for RHX100 |
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I think the same could work for crc64 on rv64, but I am not a crc expert, and I can't immediately find a source about it. So I'll leave it for this, don't want to make any mistakes in checksums. |
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let's wait to merge this for the first jenkins run on the gcc16 arc-2026.09 |
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Aug 4, 2026
As shown in the code snippet in the RISC-V bitmanip spec v0.93 in section 2.8. It is not present in the ratified spec, but the clmulr definition has not changed between them. This significantly improves performance for rv32 processors that have the zbc extension. __builtin_rev_crc32_data32 (crc, data, poly) on rv32_zbc now generates: li a4,-150925312 xor a0,a0,a1 addi a4,a4,1601 li a5,-306675712 clmul a0,a0,a4 addi a5,a5,800 clmulr a0,a0,a5 which is more compact and faster than the previous approach which generates more than 300 lines of assembly and table data. Signed-off-by: Loeka Rogge <loeka.rogge@globalfoundries.com>
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As shown in the code snippet in the RISC-V bitmanip spec v0.93 in section 2.8. It is not present in the ratified spec, but the clmulr definition has not changed between them.
This significantly improves performance for rv32 processors that have the zbc extension.
__builtin_rev_crc32_data32 (crc, data, poly) on rv32_zbc now generates:
li a4,-150925312
xor a0,a0,a1
addi a4,a4,1601
li a5,-306675712
clmul a0,a0,a4
addi a5,a5,800
clmulr a0,a0,a5
which is more compact and faster than the previous approach which generates more than 300 lines of assembly and table data.