Design Verification Engineer| RISC-V Enthusiast | FPGA & SoC Hobbyist
- Pakistan
- in/fahad-hussain-a8b80b266
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GCD_systemVerilog
GCD_systemVerilog PublicA 32bit GCD implementation in SystemVerilog.
SystemVerilog 1
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Factorial_SystemVerilog
Factorial_SystemVerilog PublicA 32bit Factorial implementation in System Verilog
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serv-fpu-extension
serv-fpu-extension PublicFPU extension for the SERV RISC-V core via the extension interface
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Verification-of-AXI-APB-Bus
Verification-of-AXI-APB-Bus PublicUVM Based Verification of AXI-APB Bus
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