sb: el: sync 2026.25.01 and 2026.27.01 release updates#2743
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Summary: - Add shell command to show CPLD power good status - Support EVB-specific P3V3 OSFP power good check Test Plan: - Build code: Pass
Summary: - Modify dc on/off ISR to switch A12 pin between GPIO and CS1. - Pull CS1, NUWA0_CNV, NUWA0_CNV high before ADC polling to avoid CS1 interfering with CS0 communication. Test Plan: - Build code: Pass
Summary: * Change NUWA0/NUWA1 CHIP_STRAP_0/1 from STRAP_TYPE_CPLD to STRAP_TYPE_GPIO * Use GPIO number instead of CPLD offset 0x1a for NUWA chip strap control * Add GPIO read/write handling in bootstrap strap flow * Keep existing CPLD and IO expander strap behavior unchanged Test Plan: * Build code: Pass * Function check: Pass
Summary: - Increase board product buffer size from 32 to 64 bytes - Decode board product field directly into destination buffer - Prevent board product string truncation when FRU field length exceeds 31 bytes Test Plan: - Build code: Pass - Verify FRU information parsing: Pass - Verify long board product string is displayed correctly: Pass
Summary: - Remove unused `PLL_VDDA15_HBM` power sequence and PWRGD mapping - Add `P1V2_PLL_VDDA_OWL` and `P1V2_PLL_VDDA_SOC` sequence entries - Rename `VDDQC` related power sequence and PWRGD names to `VDDC` - Add `VDDQ` related sequence and PWRGD mapping into power control flow - Align `steps_on[]` and power good tables with current platform rail definition Test Plan: - Build code: Pass
Summary: - Update power sequence mapping in `shell_plat_power_sequence.c` - Add `VDDQ` related entries to sequence and PWRGD tables - Rename `VDDQC` related entries to `VDDC` - Update PLL VDDA related rail mapping to match current platform definition Test Plan: - Build code: Pass
Summary: - Update `VR_POWER_FAULT_4_REG` log strings in `shell_plat_power_sequence.c` - Change `PLL_VDDA15_HBM*` related log names to `VDDQ_HBM*` and `P1V2_PLL_VDDA_*` - Align fault event log output with current rail naming Test Plan: - Build code: Pass
Summary: - Fix JTAG MUX comment to match hardware mapping. Test Plan: - Build code: Pass
Summary: - Increase board product buffer size from 64 to 48 bytes - Increase board custom data buffer size from 32 to 48 bytes - Prevent truncation of longer FRU board information fields Test Plan: - Build code: Pass - Verify FRU information parsing: Pass - Verify board product and custom data fields are displayed correctly: Pass Related-to: 4c64b54
Summary: - Add VDDQ_HBM0246 SMBAlert event entry to the CPLD info table - Handle VDDQ_HBM0246 SMBAlert events separately from HBM CATTRIP - Trigger VR temperature status check for the new SMBAlert source - Assert ASIC_VR_HOT when a VR temperature fault is detected Test Plan: - Build code: Pass
Summary: - Add `OWL_W_SOC_CATTRIP_R` `OWL_E_SOC_CATTRIP_R` `HAMSA_CATTRIP_SITE_R` monitoring and send event to bmc when triggered Test Plan: - Build code: Pass - Blackbox test: Pass
Summary: - Change GPIO03 configuration from open-drain to push-pull Test Plan: - Build code: Pass
Summary: - Move power_good_status struct, and power_good_status_type enum from .c files into shell_arke_power.h - Remove duplicate table and definitions in shell_power_good_status.c, reuse power_good_status_table_for_steps_on - Replace direct array indexing in cmd_arke_steps_on with find_pwrgd_entry() lookup Test Plan: - Build code: Pass
Summary: - Version commit for 2026.25.01. Test Plan: - Build code: Pass - Function check: Pass
Summary: - Rename VDDQC-related SMBALRT event names to VDDC - Add `ARKE_VDDC_VDDQ_1357_SMBALRT_N` - Add `ARKE_VDDC_VDDQ_0246_SMBALRT_N` - Align SMBALRT event source definitions with current rail naming Test Plan: - Build code: Pass
Summary: - Add `ARKE_VDDQ_1357_SMBALRT_N` event entry in `vr_fault_table` - Add `ARKE_VDDQ_0246_SMBALRT_N` event entry in `vr_fault_table` - Extend VR SMBALRT event source mapping for VDDQ rails Test Plan: - Build code: Pass
Summary: - Update `plat_poll_cpld_info_table()` to check only SMBALRT bits covered by `bit_check_mask` - Skip unrelated SMBALRT bits during CPLD fault polling - Move `vr_hot_switch` variable outside the inner loop for cleaner handling Test Plan: - Build code: Pass
Summary: - Add VDDQ HBM0246 SMBALRT mapping in `vr_error_callback_info_table` - Update `plat_poll_cpld_info_table()` to check only changed SMBALRT bits - Extend `get_error_data()` to handle the new SMBALRT source correctly - Reduce unnecessary SMBALRT processing for unchanged bits Test Plan: - Build code: Pass
Summary: - Update `arke_event_source` enum - Rename `ARKE_MAX_N_VDDRXTX_SMBALRT_N` to `ARKE_MAX_N_SMBALRT_N` Test Plan: - Build code: Pass
Summary: - Update SMBALRT-related names in `cpld_bit_name_table` - Map `VDDQ_0246_SMBALRT_N` to `VR_SMBUS_ALERT_EVENT_LOG_REG` - Map `VDDQ_1357_SMBALRT_N` to `ASIC_CATTRIP_REG` Test Plan: - Build code: Pass
Summary: - Modify blackbox VR SMBALRT - Show SMBALRT rails name and STATUS_WORD Test Plan: - Build code: Pass
Summary: - Update UCR and LCR threshold settings for ARKE sensors - Adjust temperature, voltage, current, and power sensor threshold values - Align sensor threshold configuration with latest platform requirement Test Plan: - Build code: Pass - Verify updated sensor thresholds through `sensor_threshold get all`
Summary: - Enable INA238 Sensor Polling Test Plan: - Build code: Pass
Summary: - Add `ENABLE_INA238` define in `plat_def` - Add INA238 address and init arguments - Add `SENSOR_NUM_INA238_VOLT_VBUS_A` sensor entry Test Plan: - Build code: Pass
Summary: - Move `SENSOR_NUM_INA238_VOLT_VBUS_A`, `SENSOR_NUM_INA238_CURR_A`, and `SENSOR_NUM_INA238_PWR_W` from `plat_pldm_sensor_evb_table` to `plat_pldm_sensor_quick_vr_table` - Remove `SENSOR_NUM_INA238_VOLT_VSHUNT_A` - Add slot-based INA238 address selection - Define `INA238_ADDR_EVB`, `INA238_ADDR_0`, `INA238_ADDR_1`, `INA238_ADDR_2`, and `INA238_ADDR_3` - Limit INA238 sensor exposure in the sensor list to `REV_ID_EVT1B` and later Test Plan: - Build code: Pass
Summary: - Add handling for VDDQ_HBM1_HBM3_HBM5_HBM7_SMBALERT_R1_N via the new CPLD register 0xC4. This register is a temporary hardware workaround for an SMBUS alert pin layout error on the current PCB revision, and will be removed once the next hardware revision corrects the layout. Test Plan: - Build code: Pass - Function test: Pass
Summary: - Enable `GPIOC0` for `U626_OE` - Configure `GPIOC0` as open-drain - Set default output state to high Test Plan: - Build code: Pass
Summary: - Version commit for 2026.27.01. Test Plan: - Build code: Pass - Function check: Pass
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This pull request has been imported. If you are a Meta employee, you can view this in D111200199. (Because this pull request was imported automatically, there will not be any future comments.) |
Summary: - Fix code formatting issues with clang-format - Align source formatting with project style Test Plan: - Build code: Pass
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Summary
This PR syncs the Santa Barbara Electra release updates from 2026.25.01 through 2026.27.01.
The changes mainly cover CPLD / SMBALRT event handling updates, power sequence and power-good mapping updates, INA238 sensor support, GPIO and hardware configuration updates, FRU string handling improvements, and related shell/debug enhancements.
Features
Add shell command for CPLD power good status
Update ADC mechanism for DC on/off pin switching and CS conflict handling
Change NUWA chip strap control from CPLD to GPIO
Update power sequence, PWRGD mapping, and related shell display
VDDQrelated sequence and PWRGD entriesVDDQCrelated names toVDDCPLL_VDDArelated mapping and log stringsImprove FRU / board information handling
Add and refine SMBALRT / fault event handling
CPLD_UNEXPECTED_VAL_TRIGGER_CAUSEblackbox event to show SMBALRT rail names andSTATUS_WORD0xC4Update GPIO and hardware-related configuration
GPIO03from open-drain to push-pullGPIOC0U626_OEas open-drain with default highAdd INA238 support and related updates
REV_ID_EVT1Band laterUpdate sensor threshold configuration
Included releases
Test Plan
sensor_threshold get all