hw/xtensa/esp32s3: reset CPENABLE to 0xff to match silicon (QEMU-294)#155
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hw/xtensa/esp32s3: reset CPENABLE to 0xff to match silicon (QEMU-294)#155mandreev57 wants to merge 1 commit into
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ESP32-S3 (LX7) silicon resets CPENABLE to 0xff — verified directly on ESP32-S3 hardware: an `rsr.cpenable` as the first instruction of `main` reads 0xff on silicon, and 0x00 in qemu-system-xtensa (esp-develop-9.2.2-20260417). Guest firmware that depends on the silicon contract — including any exception path that spills f0..f15 before establishing CPENABLE — works on hardware but hangs in emulation. xtensa-lx-rt 0.21 with `float-save-restore` (enabled by default in esp-hal 1.0) does exactly that, so the first floating-point op in a Rust ESP32-S3 binary re-raises Cp0Disabled through the user-exception vector indefinitely. target/xtensa/cpu.c writes CPENABLE = 0xff only inside the CONFIG_USER_ONLY branch of xtensa_cpu_reset_hold. Rather than change the generic Xtensa system-mode reset (which would also affect the upstream sim/xtfpga/virt boards), restore the vendor reset value right after cpu_reset() in the ESP32-S3 SoC reset handler. No impact on non-Espressif Xtensa machines. Reported and reproduced in espressif#154. Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com> Signed-off-by: Mikhail Andreev <mikhail.andreev.57@gmail.com>
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Fixes #154.
ESP32-S3 (LX7) silicon resets
CPENABLEto0xff— directlymeasured on ESP32-S3 with
rsr.cpenableas the first instructionin
main(0xffon hardware,0x00underesp-develop-9.2.2-20260417).xtensa_cpu_reset_holdalready writesCPENABLE = 0xff, but only inthe
CONFIG_USER_ONLYbranch, soqemu-system-xtensaboots with theISA default of
0. Guest firmware that assumes the silicon contracthangs on the first floating-point instruction —
Cp0Disabled(cause32) re-raises through the user-exception vector, which itself spills
f0..f15before CPENABLE is set (this is whatxtensa-lx-rt 0.21with
float-save-restoredoes; that path is enabled by default inesp-hal 1.0).Approach
Rather than make the unconditional change in
target/xtensa/cpu.c— which would change the reset value for the upstream
sim/xtfpga/virtXtensa boards too — this patch writes thevendor reset value right after
cpu_reset()in the ESP32-S3 SoCreset handler (
esp32s3_soc_reset). Scope is limited to the chipwhere the silicon value has been directly measured.
ESP32 (LX6,
hw/xtensa/esp32.c) and ESP32-S2 almost certainly behavethe same way —
xtensa_cpu_reset_hold's user-mode branch sets0xffunconditionally and the Espressif toolchain assumes it — butI have not directly measured
rsr.cpenableafter reset on thosechips yet. The same one-line write should be added under each
corresponding
cpu_reset()once that's confirmed. (hw/xtensa/esp32s2.cdoes not exist in this fork today.)
Verification
Against the minimal repro in #154, the FP loop now completes instead
of hanging silently. No change for guest binaries that already set
CPENABLEexplicitly.