C6 h2 retention registers

common_patches/plic.yaml

@@ -5,7 +5,7 @@ _add:
     groupName: PLIC
     addressBlock:
       offset: 0x0
-      size: 0x98
+      size: 0x400
       usage: registers
     registers:
       MXINT_ENABLE:
@@ -87,14 +87,25 @@ _add:
             bitOffset: 0
             bitWidth: 32
             access: read-write
+      MXINT_CONF:
+        description: "PLIC MX Interrupt Configuration Register (PLIC_MXINT_CONF_REG)"
+        addressOffset: 0x03FC
+        size: 32
+        access: read-write
+        fields:
+          CPU_MXINT_CONF:
+            description: ""
+            bitOffset: 0
+            bitWidth: 32
+            access: read-write
 
   PLIC_UX:
     description: PLIC Peripheral
     baseAddress: 0x20001400
     groupName: PLIC
     addressBlock:
       offset: 0x0
-      size: 0x98
+      size: 0x400
       usage: registers
     registers:
       UXINT_ENABLE:
@@ -176,3 +187,14 @@ _add:
             bitOffset: 0
             bitWidth: 32
             access: read-write
+      UXINT_CONF:
+        description: "PLIC UX Interrupt Configuration Register (PLIC_UXINT_CONF_REG)"
+        addressOffset: 0x03FC
+        size: 32
+        access: read-write
+        fields:
+          CPU_UXINT_CONF:
+            description: ""
+            bitOffset: 0
+            bitWidth: 32
+            access: read-write

common_patches/spi1_mspi_shared.yaml

@@ -0,0 +1,95 @@
+_derive:
+  SPI_SMEM_DDR:
+    _from: SPI0.SPI_SMEM_DDR
+    addressOffset: 0xD8
+    description: MSPI external RAM DDR mode control register
+
+  SPI_FMEM_PMS%s_ATTR:
+    _from: SPI0.SPI_FMEM_PMS%s_ATTR
+    addressOffset: 0x100
+    dim: 4
+    dimIncrement: 0x4
+  SPI_FMEM_PMS%s_ADDR:
+    _from: SPI0.SPI_FMEM_PMS%s_ADDR
+    addressOffset: 0x110
+    dim: 4
+    dimIncrement: 0x4
+  SPI_FMEM_PMS%s_SIZE:
+    _from: SPI0.SPI_FMEM_PMS%s_SIZE
+    addressOffset: 0x120
+    dim: 4
+    dimIncrement: 0x4
+  SPI_SMEM_PMS%s_ATTR:
+    _from: SPI0.SPI_SMEM_PMS%s_ATTR
+    addressOffset: 0x130
+    dim: 4
+    dimIncrement: 0x4
+  SPI_SMEM_PMS%s_ADDR:
+    _from: SPI0.SPI_SMEM_PMS%s_ADDR
+    addressOffset: 0x140
+    dim: 4
+    dimIncrement: 0x4
+  SPI_SMEM_PMS%s_SIZE:
+    _from: SPI0.SPI_SMEM_PMS%s_SIZE
+    addressOffset: 0x150
+    dim: 4
+    dimIncrement: 0x4
+
+  PMS_REJECT:
+    _from: SPI0.PMS_REJECT
+    addressOffset: 0x164
+  ECC_CTRL:
+    _from: SPI0.ECC_CTRL
+    addressOffset: 0x168
+  ECC_ERR_ADDR:
+    _from: SPI0.ECC_ERR_ADDR
+    addressOffset: 0x16C
+  AXI_ERR_ADDR:
+    _from: SPI0.AXI_ERR_ADDR
+    addressOffset: 0x170
+    description: MSPI AXI request error address
+  SPI_SMEM_ECC_CTRL:
+    _from: SPI0.SPI_SMEM_ECC_CTRL
+    addressOffset: 0x174
+
+  DIN_MODE:
+    _from: SPI0.DIN_MODE
+    addressOffset: 0x184
+  DIN_NUM:
+    _from: SPI0.DIN_NUM
+    addressOffset: 0x188
+  DOUT_MODE:
+    _from: SPI0.DOUT_MODE
+    addressOffset: 0x18C
+  SPI_SMEM_TIMING_CALI:
+    _from: SPI0.SPI_SMEM_TIMING_CALI
+    addressOffset: 0x190
+  SPI_SMEM_DIN_MODE:
+    _from: SPI0.SPI_SMEM_DIN_MODE
+    addressOffset: 0x194
+  SPI_SMEM_DIN_NUM:
+    _from: SPI0.SPI_SMEM_DIN_NUM
+    addressOffset: 0x198
+  SPI_SMEM_DOUT_MODE:
+    _from: SPI0.SPI_SMEM_DOUT_MODE
+    addressOffset: 0x19C
+  SPI_SMEM_AC:
+    _from: SPI0.SPI_SMEM_AC
+    addressOffset: 0x1A0
+
+  MMU_ITEM_CONTENT:
+    _from: SPI0.MMU_ITEM_CONTENT
+    addressOffset: 0x37C
+  MMU_ITEM_INDEX:
+    _from: SPI0.MMU_ITEM_INDEX
+    addressOffset: 0x380
+  MMU_POWER_CTRL:
+    _from: SPI0.MMU_POWER_CTRL
+    addressOffset: 0x384
+
+  REGISTERRND_ECO_HIGH:
+    _from: SPI0.REGISTERRND_ECO_HIGH
+    addressOffset: 0x3F0
+  REGISTERRND_ECO_LOW:
+    _from: SPI0.REGISTERRND_ECO_LOW
+    addressOffset: 0x3F4

esp32c6/src/plic_mx.rs

@@ -9,6 +9,8 @@ pub struct RegisterBlock {
     mxint_pri: [MXINT_PRI; 32],
     mxint_thresh: MXINT_THRESH,
     mxint_claim: MXINT_CLAIM,
+    _reserved7: [u8; 0x0364],
+    mxint_conf: MXINT_CONF,
 }
 impl RegisterBlock {
     #[doc = "0x00 - PLIC MX Interrupt Enable Register"]
@@ -212,6 +214,11 @@ impl RegisterBlock {
     pub const fn mxint_claim(&self) -> &MXINT_CLAIM {
         &self.mxint_claim
     }
+    #[doc = "0x3fc - PLIC MX Interrupt Configuration Register (PLIC_MXINT_CONF_REG)"]
+    #[inline(always)]
+    pub const fn mxint_conf(&self) -> &MXINT_CONF {
+        &self.mxint_conf
+    }
 }
 #[doc = "MXINT_ENABLE (rw) register accessor: PLIC MX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_enable`] module"]
 pub type MXINT_ENABLE = crate::Reg<mxint_enable::MXINT_ENABLE_SPEC>;
@@ -241,3 +248,7 @@ pub mod mxint_thresh;
 pub type MXINT_CLAIM = crate::Reg<mxint_claim::MXINT_CLAIM_SPEC>;
 #[doc = "PLIC MX Interrupt Claim Register"]
 pub mod mxint_claim;
+#[doc = "MXINT_CONF (rw) register accessor: PLIC MX Interrupt Configuration Register (PLIC_MXINT_CONF_REG)\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@mxint_conf`] module"]
+pub type MXINT_CONF = crate::Reg<mxint_conf::MXINT_CONF_SPEC>;
+#[doc = "PLIC MX Interrupt Configuration Register (PLIC_MXINT_CONF_REG)"]
+pub mod mxint_conf;

esp32c6/src/plic_mx/mxint_conf.rs

@@ -0,0 +1,43 @@
+#[doc = "Register `MXINT_CONF` reader"]
+pub type R = crate::R<MXINT_CONF_SPEC>;
+#[doc = "Register `MXINT_CONF` writer"]
+pub type W = crate::W<MXINT_CONF_SPEC>;
+#[doc = "Field `CPU_MXINT_CONF` reader - "]
+pub type CPU_MXINT_CONF_R = crate::FieldReader<u32>;
+#[doc = "Field `CPU_MXINT_CONF` writer - "]
+pub type CPU_MXINT_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31"]
+    #[inline(always)]
+    pub fn cpu_mxint_conf(&self) -> CPU_MXINT_CONF_R {
+        CPU_MXINT_CONF_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("MXINT_CONF")
+            .field("cpu_mxint_conf", &self.cpu_mxint_conf())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31"]
+    #[inline(always)]
+    pub fn cpu_mxint_conf(&mut self) -> CPU_MXINT_CONF_W<'_, MXINT_CONF_SPEC> {
+        CPU_MXINT_CONF_W::new(self, 0)
+    }
+}
+#[doc = "PLIC MX Interrupt Configuration Register (PLIC_MXINT_CONF_REG)\n\nYou can [`read`](crate::Reg::read) this register and get [`mxint_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`mxint_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct MXINT_CONF_SPEC;
+impl crate::RegisterSpec for MXINT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`mxint_conf::R`](R) reader structure"]
+impl crate::Readable for MXINT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`mxint_conf::W`](W) writer structure"]
+impl crate::Writable for MXINT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+}
+#[doc = "`reset()` method sets MXINT_CONF to value 0"]
+impl crate::Resettable for MXINT_CONF_SPEC {}

esp32c6/src/plic_ux.rs

@@ -9,6 +9,8 @@ pub struct RegisterBlock {
     uxint_pri: [UXINT_PRI; 32],
     uxint_thresh: UXINT_THRESH,
     uxint_claim: UXINT_CLAIM,
+    _reserved7: [u8; 0x0364],
+    uxint_conf: UXINT_CONF,
 }
 impl RegisterBlock {
     #[doc = "0x00 - PLIC UX Interrupt Enable Register"]
@@ -212,6 +214,11 @@ impl RegisterBlock {
     pub const fn uxint_claim(&self) -> &UXINT_CLAIM {
         &self.uxint_claim
     }
+    #[doc = "0x3fc - PLIC UX Interrupt Configuration Register (PLIC_UXINT_CONF_REG)"]
+    #[inline(always)]
+    pub const fn uxint_conf(&self) -> &UXINT_CONF {
+        &self.uxint_conf
+    }
 }
 #[doc = "UXINT_ENABLE (rw) register accessor: PLIC UX Interrupt Enable Register\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_enable::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_enable::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_enable`] module"]
 pub type UXINT_ENABLE = crate::Reg<uxint_enable::UXINT_ENABLE_SPEC>;
@@ -241,3 +248,7 @@ pub mod uxint_thresh;
 pub type UXINT_CLAIM = crate::Reg<uxint_claim::UXINT_CLAIM_SPEC>;
 #[doc = "PLIC UX Interrupt Claim Register"]
 pub mod uxint_claim;
+#[doc = "UXINT_CONF (rw) register accessor: PLIC UX Interrupt Configuration Register (PLIC_UXINT_CONF_REG)\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_conf::R`]. You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_conf::W`]. You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [`mod@uxint_conf`] module"]
+pub type UXINT_CONF = crate::Reg<uxint_conf::UXINT_CONF_SPEC>;
+#[doc = "PLIC UX Interrupt Configuration Register (PLIC_UXINT_CONF_REG)"]
+pub mod uxint_conf;

esp32c6/src/plic_ux/uxint_conf.rs

@@ -0,0 +1,43 @@
+#[doc = "Register `UXINT_CONF` reader"]
+pub type R = crate::R<UXINT_CONF_SPEC>;
+#[doc = "Register `UXINT_CONF` writer"]
+pub type W = crate::W<UXINT_CONF_SPEC>;
+#[doc = "Field `CPU_UXINT_CONF` reader - "]
+pub type CPU_UXINT_CONF_R = crate::FieldReader<u32>;
+#[doc = "Field `CPU_UXINT_CONF` writer - "]
+pub type CPU_UXINT_CONF_W<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31"]
+    #[inline(always)]
+    pub fn cpu_uxint_conf(&self) -> CPU_UXINT_CONF_R {
+        CPU_UXINT_CONF_R::new(self.bits)
+    }
+}
+#[cfg(feature = "impl-register-debug")]
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        f.debug_struct("UXINT_CONF")
+            .field("cpu_uxint_conf", &self.cpu_uxint_conf())
+            .finish()
+    }
+}
+impl W {
+    #[doc = "Bits 0:31"]
+    #[inline(always)]
+    pub fn cpu_uxint_conf(&mut self) -> CPU_UXINT_CONF_W<'_, UXINT_CONF_SPEC> {
+        CPU_UXINT_CONF_W::new(self, 0)
+    }
+}
+#[doc = "PLIC UX Interrupt Configuration Register (PLIC_UXINT_CONF_REG)\n\nYou can [`read`](crate::Reg::read) this register and get [`uxint_conf::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`uxint_conf::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct UXINT_CONF_SPEC;
+impl crate::RegisterSpec for UXINT_CONF_SPEC {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`uxint_conf::R`](R) reader structure"]
+impl crate::Readable for UXINT_CONF_SPEC {}
+#[doc = "`write(|w| ..)` method takes [`uxint_conf::W`](W) writer structure"]
+impl crate::Writable for UXINT_CONF_SPEC {
+    type Safety = crate::Unsafe;
+}
+#[doc = "`reset()` method sets UXINT_CONF to value 0"]
+impl crate::Resettable for UXINT_CONF_SPEC {}