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Xtensa PSRAM driver cleanup #6198

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Xtensa PSRAM driver cleanup #6198

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5cd873a
Enable octal PSRAM for P4
bugadani Aug 25, 2026
51c7ae3
Default to 80MHz PSRAM
bugadani Aug 25, 2026
31eee7a
Deduplicate and clean up S2 and S3 PSRAM drivers
bugadani Aug 25, 2026
217fce7
Clean up ESP32
bugadani Aug 25, 2026
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566 changes: 242 additions & 324 deletions esp-hal/src/psram/esp32.rs
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5 changes: 3 additions & 2 deletions esp-hal/src/psram/esp32c5_c61.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -61,9 +61,9 @@ impl FlashFreq {
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub enum SpiRamFreq {
/// PSRAM frequency 40 MHz
#[default]
Freq40m = 40,
/// PSRAM frequency 80 MHz
/// PSRAM frequency 80 MHz. Default.
#[default]
Freq80m = 80,
}

Expand Down Expand Up @@ -121,6 +121,7 @@ impl Default for PsramConfig {
extra_dummy_len: 2,
},
ram_frequency: Default::default(),
// IDF default 80 MHz STR tuning point
ram_tuning: MspiTimingTuningParam {
spi_din_mode: 3,
spi_din_num: 1,
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10 changes: 4 additions & 6 deletions esp-hal/src/psram/esp32p4.rs
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Expand Up @@ -14,14 +14,12 @@ mod oct_hex;
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
#[instability::unstable]
pub enum PsramMode {
/// 16-line DDR, AP HEX PSRAM with MR8.x16 = 1. Default.
/// 16-line DDR. Default.
#[default]
Hex,
// TODO; selecting `Oct`
// requires the cache-side controller config (`mem_sdin_hex` /
// `mem_sdout_hex` bits) and chip MR8.x16 to flip together. Wire that
// path before exposing.
// Oct,

/// 8-line DDR.
Oct,
}

/// PSRAM configuration.
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