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Merged
MabezDev merged 1 commit into from
Aug 26, 2026
Merged

Hide XTAL32K and downstream clocks when disabled #6194

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2 changes: 1 addition & 1 deletion esp-hal/Cargo.toml
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Expand Up @@ -26,7 +26,7 @@ check-configs = [
{ features = ["unstable", "rt"], env = { ESP_HAL_CONFIG_PLACE_ANON_IN_RAM = "true", ESP_HAL_CONFIG_PLACE_RMT_DRIVER_IN_RAM = "true", ESP_HAL_CONFIG_PLACE_SPI_MASTER_DRIVER_IN_RAM = "true", ESP_HAL_CONFIG_CLEAR_CRYPTO_SECRETS = "false" } },
{ features = ["unstable", "rt"], env = { ESP_HAL_CONFIG_ENABLE_PMP = "false" }, if = 'riscv && !esp32c2 && !esp32c3' },
{ features = ["unstable", "rt"], env = { ESP_HAL_CONFIG_INIT_STACK_PTR_RANGE_CHECK = "false" } },
{ features = ["unstable", "rt"], env = { ESP_HAL_CONFIG_USE_XTAL32K = "true" }, if = 'soc_has_xtal32k_pads' },
{ features = ["unstable", "rt"], env = { ESP_HAL_CONFIG_USE_XTAL32K = "true" }, if = 'soc_has_clock_node_xtal32k_clk' },
{ features = ["unstable", "rt", "__usb_otg"], if = 'usb_otg_driver_supported' },
{ features = ["unstable", "rt", "__bluetooth"], if = 'bt_driver_supported' },
{ features = ["unstable", "rt", "__sdmmc"], if = 'sdmmc_driver_supported' },
Expand Down
2 changes: 1 addition & 1 deletion esp-hal/esp_config.yml
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Expand Up @@ -233,7 +233,7 @@ options:
When disabled (default), XTAL32K stays off so those pins can be used as hi-Z GPIO."
default:
- value: false
active: "soc_has_xtal32k_pads"
active: "soc_has_clock_node_xtal32k_clk"

- name: enable-pmp
description: "Protects additional memory regions via Physical Memory Protection (PMP). (Only RISC-V other than ESP32-C2/C3)"
Expand Down
9 changes: 6 additions & 3 deletions esp-hal/src/clock/mod.rs
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Expand Up @@ -155,7 +155,7 @@ impl RtcClock {
/// issue, or lack of 32 XTAL on board).
#[cfg(soc_has_clock_node_timg_calibration_clock)]
pub(crate) fn calibrate(cal_clk: TimgCalibrationClockConfig, slowclk_cycles: u32) -> u32 {
#[cfg(not(esp32c2))]
#[cfg(use_xtal32k)]
if cal_clk == TimgCalibrationClockConfig::Xtal32kClk {
debug!("Assuming Xtal32k has precisely 32.768kHz instead of calibrating");
let freq_hz: u64 = 32_768;
Expand Down Expand Up @@ -462,7 +462,7 @@ pub(crate) fn calibrate_rtc_slow_clock() {
let slow_clk = match unwrap!(ClockTree::with(clocks::rtc_slow_clk_config)) {
RtcSlowClkConfig::RcFast => TimgCalibrationClockConfig::RcFastDivClk,
RtcSlowClkConfig::RcSlow => TimgCalibrationClockConfig::RcSlowClk,
#[cfg(not(esp32c2))]
#[cfg(use_xtal32k)]
RtcSlowClkConfig::Xtal32k => TimgCalibrationClockConfig::Xtal32kClk,
#[cfg(esp32c2)]
RtcSlowClkConfig::OscSlow => TimgCalibrationClockConfig::Osc32kClk,
Expand All @@ -471,8 +471,11 @@ pub(crate) fn calibrate_rtc_slow_clock() {
soc_has_clock_node_lp_slow_clk => {
let slow_clk = match unwrap!(ClockTree::with(clocks::lp_slow_clk_config)) {
// on S31, clock can not be calibrated to get OSC_SLOW actual frequency
#[cfg(not(esp32s31))]
#[cfg(all(not(esp32s31), use_xtal32k))]
LpSlowClkConfig::OscSlow => TimgCalibrationClockConfig::Xtal32kClk, //?
#[cfg(all(not(esp32s31), not(use_xtal32k)))]
LpSlowClkConfig::OscSlow => TimgCalibrationClockConfig::RcSlowClk,
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => TimgCalibrationClockConfig::Xtal32kClk,
LpSlowClkConfig::RcSlow => TimgCalibrationClockConfig::RcSlowClk,
};
Expand Down
1 change: 1 addition & 0 deletions esp-hal/src/rtc_cntl/rtc/esp32c5.rs
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Expand Up @@ -114,6 +114,7 @@ impl From<LpSlowClkConfig> for ModemClockLpclkSource {
fn from(src: LpSlowClkConfig) -> Self {
match src {
LpSlowClkConfig::RcSlow => Self::RcSlow,
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => Self::XTAL32K,
LpSlowClkConfig::OscSlow => Self::EXT32K,
}
Expand Down
1 change: 1 addition & 0 deletions esp-hal/src/rtc_cntl/rtc/esp32c6.rs
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Expand Up @@ -111,6 +111,7 @@ impl From<LpSlowClkConfig> for ModemClockLpclkSource {
fn from(src: LpSlowClkConfig) -> Self {
match src {
LpSlowClkConfig::RcSlow => Self::RcSlow,
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => Self::XTAL32K,
LpSlowClkConfig::OscSlow => Self::EXT32K,
}
Expand Down
1 change: 1 addition & 0 deletions esp-hal/src/rtc_cntl/rtc/esp32c61.rs
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Expand Up @@ -114,6 +114,7 @@ impl From<LpSlowClkConfig> for ModemClockLpclkSource {
fn from(src: LpSlowClkConfig) -> Self {
match src {
LpSlowClkConfig::RcSlow => Self::RcSlow,
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => Self::XTAL32K,
LpSlowClkConfig::OscSlow => Self::EXT32K,
}
Expand Down
6 changes: 5 additions & 1 deletion esp-hal/src/rtc_cntl/rtc/esp32s31.rs
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Expand Up @@ -616,10 +616,14 @@ pub(crate) fn configure_wifi_lp_clock(config: &ClockConfig) {
w.clk_wifipwr_lp_sel_xtal32k().clear_bit();
match source {
LpSlowClkConfig::RcSlow => w.clk_wifipwr_lp_sel_osc_slow().set_bit(),
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => w.clk_wifipwr_lp_sel_xtal32k().set_bit(),
}
});
if source == LpSlowClkConfig::Xtal32k {
if cfg_select! {
use_xtal32k => source == LpSlowClkConfig::Xtal32k,
_ => false,
} {
// The WiFi 32 kHz selector feeds from the shared modem 32 kHz mux.
// MODEM_CLOCK_XTAL32K_CODE is 0 on S31.
lpcon
Expand Down
17 changes: 10 additions & 7 deletions esp-hal/src/rtc_cntl/sleep/esp32c5.rs
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Expand Up @@ -9,7 +9,7 @@ use crate::{
sleep::{SleepKind, pmu_common::SleepTimeConfig},
},
soc::{
clocks::{self, ClockTree, HpRootClkConfig, LpSlowClkConfig},
clocks::{self, ClockTree, HpRootClkConfig},
xtal32k,
},
};
Expand Down Expand Up @@ -729,12 +729,15 @@ impl RtcSleepConfig {

/// Finalize power-down flags, apply configuration based on the flags.
pub(crate) fn apply(&mut self) {
let lp_slow_uses_xtal32k = ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(LpSlowClkConfig::Xtal32k)
)
});
let lp_slow_uses_xtal32k = cfg_select! {
use_xtal32k => ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(clocks::LpSlowClkConfig::Xtal32k)
)
}),
_ => false,
};

if self.deep {
// force-disable certain power domains
Expand Down
17 changes: 10 additions & 7 deletions esp-hal/src/rtc_cntl/sleep/esp32c6.rs
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Expand Up @@ -9,7 +9,7 @@ use crate::{
sleep::{SleepKind, pmu_common::SleepTimeConfig},
},
soc::{
clocks::{self, ClockTree, LpSlowClkConfig, SocRootClkConfig},
clocks::{self, ClockTree, SocRootClkConfig},
xtal32k,
},
};
Expand Down Expand Up @@ -703,12 +703,15 @@ impl RtcSleepConfig {

/// Finalize power-down flags, apply configuration based on the flags.
pub(crate) fn apply(&mut self) {
let lp_slow_uses_xtal32k = ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(LpSlowClkConfig::Xtal32k)
)
});
let lp_slow_uses_xtal32k = cfg_select! {
use_xtal32k => ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(clocks::LpSlowClkConfig::Xtal32k)
)
}),
_ => false,
};

if self.deep {
// force-disable certain power domains
Expand Down
17 changes: 10 additions & 7 deletions esp-hal/src/rtc_cntl/sleep/esp32c61.rs
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Expand Up @@ -9,7 +9,7 @@ use crate::{
sleep::{SleepKind, pmu_common::SleepTimeConfig},
},
soc::{
clocks::{self, ClockTree, HpRootClkConfig, LpSlowClkConfig},
clocks::{self, ClockTree, HpRootClkConfig},
xtal32k,
},
};
Expand Down Expand Up @@ -731,12 +731,15 @@ impl RtcSleepConfig {

/// Finalize power-down flags, apply configuration based on the flags.
pub(crate) fn apply(&mut self) {
let lp_slow_uses_xtal32k = ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(LpSlowClkConfig::Xtal32k)
)
});
let lp_slow_uses_xtal32k = cfg_select! {
use_xtal32k => ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(clocks::LpSlowClkConfig::Xtal32k)
)
}),
_ => false,
};

if self.deep {
// force-disable certain power domains
Expand Down
17 changes: 10 additions & 7 deletions esp-hal/src/rtc_cntl/sleep/esp32h2.rs
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Expand Up @@ -9,7 +9,7 @@ use crate::{
sleep::{SleepKind, pmu_common::SleepTimeConfig},
},
soc::{
clocks::{self, ClockTree, CpuClkConfig, HpRootClkConfig, LpSlowClkConfig},
clocks::{self, ClockTree, CpuClkConfig, HpRootClkConfig},
xtal32k,
},
};
Expand Down Expand Up @@ -497,12 +497,15 @@ impl RtcSleepConfig {

/// Finalize power-down flags, apply configuration based on the flags.
pub(crate) fn apply(&mut self) {
let lp_slow_uses_xtal32k = ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(LpSlowClkConfig::Xtal32k)
)
});
let lp_slow_uses_xtal32k = cfg_select! {
use_xtal32k => ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(clocks::LpSlowClkConfig::Xtal32k)
)
}),
_ => false,
};

if self.deep {
// force-disable certain power domains
Expand Down
17 changes: 10 additions & 7 deletions esp-hal/src/rtc_cntl/sleep/esp32p4.rs
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Expand Up @@ -17,7 +17,7 @@ use crate::{
rtc::{HpAnalog, HpSysCntlReg, HpSysPower, LpAnalog, LpSysPower},
sleep::{SleepKind, pmu_common::SleepTimeConfig},
},
soc::clocks::{self, ClockTree, CpuRootClkConfig, LpSlowClkConfig},
soc::clocks::{self, ClockTree, CpuRootClkConfig},
};

// ----------------------------------------------------------------------------
Expand Down Expand Up @@ -878,12 +878,15 @@ impl RtcSleepConfig {

/// Finalize power-down flags, apply configuration based on the flags.
pub(crate) fn apply(&mut self) {
let lp_slow_uses_xtal32k = ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(LpSlowClkConfig::Xtal32k)
)
});
let lp_slow_uses_xtal32k = cfg_select! {
use_xtal32k => ClockTree::with(|clocks| {
matches!(
clocks::lp_slow_clk_config(clocks),
Some(clocks::LpSlowClkConfig::Xtal32k)
)
}),
_ => false,
};

if self.deep {
self.pd_flags.set_pd_top(true);
Expand Down
7 changes: 6 additions & 1 deletion esp-hal/src/soc/esp32/clocks.rs
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Expand Up @@ -17,10 +17,12 @@

use esp_rom_sys::rom::{ets_delay_us, ets_update_cpu_frequency_rom};

#[cfg(use_xtal32k)]
use crate::peripherals::RTC_IO;
use crate::{
clock::RtcClock,
efuse::VOL_LEVEL_HP_INV,
peripherals::{APB_CTRL, LPWR, RMT, RTC_IO, SYSTEM, TIMG0},
peripherals::{APB_CTRL, LPWR, RMT, SYSTEM, TIMG0},
rtc_cntl::Rtc,
soc::{regi2c, xtal32k},
time::Rate,
Expand Down Expand Up @@ -595,6 +597,7 @@ fn enable_apb_clk_80m_impl(_clocks: &mut ClockTree, _en: bool) {

// XTAL32K_CLK

#[cfg(use_xtal32k)]
fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, en: bool) {
// RTCIO could be configured to allow an external oscillator to be used. We could model this
// with a MUX, probably, but this is omitted for now for simplicity.
Expand Down Expand Up @@ -671,6 +674,7 @@ fn configure_rtc_slow_clk_impl(
) {
LPWR::regs().clk_conf().modify(|_, w| match new_config {
RtcSlowClkConfig::RcSlow => w.ana_clk_rtc_sel().slow_ck(),
#[cfg(use_xtal32k)]
RtcSlowClkConfig::Xtal32k => w.ana_clk_rtc_sel().ck_xtal_32k(),
RtcSlowClkConfig::RcFast => w.ana_clk_rtc_sel().ck8m_d256_out(),
});
Expand Down Expand Up @@ -728,6 +732,7 @@ fn configure_timg_calibration_clock_impl(
w.rtc_cali_clk_sel().bits(match new_config {
TimgCalibrationClockConfig::RcSlowClk => 0,
TimgCalibrationClockConfig::RcFastDivClk => 1,
#[cfg(use_xtal32k)]
TimgCalibrationClockConfig::Xtal32kClk => 2,
})
});
Expand Down
11 changes: 9 additions & 2 deletions esp-hal/src/soc/esp32c3/clocks.rs
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Expand Up @@ -252,6 +252,7 @@ fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, en: bool) {

// XTAL32K_CLK

#[cfg(use_xtal32k)]
fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, en: bool) {
// RTCIO could be configured to allow an external oscillator to be used. We could model this
// with a MUX, probably, but this is omitted for now for simplicity.
Expand Down Expand Up @@ -487,6 +488,7 @@ fn configure_rtc_slow_clk_impl(
LPWR::regs().clk_conf().modify(|_, w| unsafe {
// TODO: variants should be in PAC
w.ana_clk_rtc_sel().bits(match new_config {
#[cfg(use_xtal32k)]
RtcSlowClkConfig::Xtal32k => 1,
RtcSlowClkConfig::RcSlow => 0,
RtcSlowClkConfig::RcFast => 2,
Expand Down Expand Up @@ -535,8 +537,12 @@ fn configure_low_power_clk_impl(
.bit(new_config == LowPowerClkConfig::RtcSlow);
w.lpclk_sel_xtal()
.bit(new_config == LowPowerClkConfig::Xtal);
w.lpclk_sel_xtal32k()
.bit(new_config == LowPowerClkConfig::Xtal32k)
w.lpclk_sel_xtal32k().bit({
cfg_select! {
use_xtal32k => new_config == LowPowerClkConfig::Xtal32k,
_ => false,
}
})
});
}

Expand Down Expand Up @@ -575,6 +581,7 @@ fn configure_timg_calibration_clock_impl(
w.rtc_cali_clk_sel().bits(match new_config {
TimgCalibrationClockConfig::RcSlowClk => 0,
TimgCalibrationClockConfig::RcFastDivClk => 1,
#[cfg(use_xtal32k)]
TimgCalibrationClockConfig::Xtal32kClk => 2,
})
});
Expand Down
3 changes: 3 additions & 0 deletions esp-hal/src/soc/esp32c5/clocks.rs
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Expand Up @@ -227,6 +227,7 @@ fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, en: bool) {

// XTAL32K_CLK

#[cfg(use_xtal32k)]
fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, en: bool) {
LP_CLKRST::regs()
.clk_to_hp()
Expand Down Expand Up @@ -440,6 +441,7 @@ fn configure_lp_slow_clk_impl(
LP_CLKRST::regs().lp_clk_conf().modify(|_, w| unsafe {
w.slow_clk_sel().bits(match new_config {
LpSlowClkConfig::RcSlow => 0,
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => 1,
// LpSlowClkConfig::Ext32k => 2,
LpSlowClkConfig::OscSlow => 3,
Expand Down Expand Up @@ -496,6 +498,7 @@ fn configure_timg_calibration_clock_impl(
PCR::regs().ctrl_32k_conf().modify(|_, w| unsafe {
w._32k_sel().bits(match new_config {
TimgCalibrationClockConfig::OscSlowClk => 0,
#[cfg(use_xtal32k)]
TimgCalibrationClockConfig::Xtal32kClk => 1,
// TimgCalibrationClockConfig::Ext32kClk => 2,
TimgCalibrationClockConfig::RcSlowClk => 3,
Expand Down
3 changes: 3 additions & 0 deletions esp-hal/src/soc/esp32c6/clocks.rs
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Expand Up @@ -210,6 +210,7 @@ fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, en: bool) {

// XTAL32K_CLK

#[cfg(use_xtal32k)]
fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, en: bool) {
LP_CLKRST::regs().xtal32k().write(|w| unsafe {
w.dac_xtal32k().bits(3);
Expand Down Expand Up @@ -539,6 +540,7 @@ fn configure_lp_slow_clk_impl(
) {
LP_CLKRST::regs().lp_clk_conf().modify(|_, w| unsafe {
w.slow_clk_sel().bits(match new_config {
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => 1,
LpSlowClkConfig::RcSlow => 0,
LpSlowClkConfig::OscSlow => 2,
Expand All @@ -562,6 +564,7 @@ fn configure_timg_calibration_clock_impl(
w.rtc_cali_clk_sel().bits(match new_config {
TimgCalibrationClockConfig::RcSlowClk => 0,
TimgCalibrationClockConfig::RcFastDivClk => 1,
#[cfg(use_xtal32k)]
TimgCalibrationClockConfig::Xtal32kClk => 2,
})
});
Expand Down
3 changes: 3 additions & 0 deletions esp-hal/src/soc/esp32c61/clocks.rs
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Expand Up @@ -179,6 +179,7 @@ fn enable_rc_fast_clk_impl(_clocks: &mut ClockTree, en: bool) {

// XTAL32K_CLK

#[cfg(use_xtal32k)]
fn enable_xtal32k_clk_impl(_clocks: &mut ClockTree, en: bool) {
LP_CLKRST::regs()
.clk_to_hp()
Expand Down Expand Up @@ -375,6 +376,7 @@ fn configure_lp_slow_clk_impl(
LP_CLKRST::regs().lp_clk_conf().modify(|_, w| unsafe {
w.slow_clk_sel().bits(match new_config {
LpSlowClkConfig::RcSlow => 0,
#[cfg(use_xtal32k)]
LpSlowClkConfig::Xtal32k => 1,
// LpSlowClkConfig::Ext32k => 2,
LpSlowClkConfig::OscSlow => 3,
Expand All @@ -396,6 +398,7 @@ fn configure_timg_calibration_clock_impl(
PCR::regs().ctrl_32k_conf().modify(|_, w| unsafe {
w._32k_sel().bits(match new_config {
TimgCalibrationClockConfig::OscSlowClk => 0,
#[cfg(use_xtal32k)]
TimgCalibrationClockConfig::Xtal32kClk => 1,
// TimgCalibrationClockConfig::Ext32kClk => 2,
TimgCalibrationClockConfig::RcSlowClk => 3,
Expand Down
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