Skip to content

S31: Correctly model MEM_CLK and SYS_CLK #6190

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
bugadani wants to merge 1 commit into
base: main
Choose a base branch
from
Open

S31: Correctly model MEM_CLK and SYS_CLK #6190

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
34 changes: 26 additions & 8 deletions esp-hal/src/soc/esp32s31/clocks.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -41,8 +41,9 @@ impl CpuClock {
const PRESET_160: ClockConfig = ClockConfig {
cpu_root_clk: Some(CpuRootClkConfig::Cpll),
cpu_clk: Some(CpuClkConfig::new(1)),
ahb_clk: Some(AhbClkConfig::new(1)),
apb_clk: Some(ApbClkConfig::new(1)),
mem_clk: Some(MemClkConfig::new(0)), // Max 160 MHz
sys_clk: Some(SysClkConfig::new(1)), // Max ~320/3 MHz
apb_clk: Some(ApbClkConfig::new(1)), // MAX ~320/6MHz
lp_fast_clk: Some(LpFastClkConfig::RcFast),
lp_slow_clk: Some(xtal32k::default_lp_slow_clk()),
iomux_function_clock: Some(IomuxFunctionClockConfig::new(
Expand All @@ -54,8 +55,9 @@ impl CpuClock {
const PRESET_240: ClockConfig = ClockConfig {
cpu_root_clk: Some(CpuRootClkConfig::PllF240m),
cpu_clk: Some(CpuClkConfig::new(0)),
ahb_clk: Some(AhbClkConfig::new(2)),
apb_clk: Some(ApbClkConfig::new(1)),
mem_clk: Some(MemClkConfig::new(1)), // Max 160 MHz
sys_clk: Some(SysClkConfig::new(2)), // Max ~320/3 MHz
apb_clk: Some(ApbClkConfig::new(1)), // MAX ~320/6MHz
lp_fast_clk: Some(LpFastClkConfig::RcFast),
lp_slow_clk: Some(xtal32k::default_lp_slow_clk()),
iomux_function_clock: Some(IomuxFunctionClockConfig::new(
Expand All @@ -67,8 +69,9 @@ impl CpuClock {
const PRESET_320: ClockConfig = ClockConfig {
cpu_root_clk: Some(CpuRootClkConfig::Cpll),
cpu_clk: Some(CpuClkConfig::new(0)),
ahb_clk: Some(AhbClkConfig::new(2)),
apb_clk: Some(ApbClkConfig::new(1)),
mem_clk: Some(MemClkConfig::new(1)), // Max 160 MHz
sys_clk: Some(SysClkConfig::new(2)), // Max ~320/3 MHz
apb_clk: Some(ApbClkConfig::new(1)), // MAX ~320/6MHz
lp_fast_clk: Some(LpFastClkConfig::RcFast),
lp_slow_clk: Some(xtal32k::default_lp_slow_clk()),
iomux_function_clock: Some(IomuxFunctionClockConfig::new(
Expand Down Expand Up @@ -420,11 +423,26 @@ fn configure_cpu_clk_impl(_clocks: &mut ClockTree, _old: Option<CpuClkConfig>, n
}
}

fn enable_ahb_clk_impl(_clocks: &mut ClockTree, _en: bool) {
// MEM_CLK

fn enable_mem_clk_impl(_clocks: &mut ClockTree, _en: bool) {
// Nothing to do here
}

fn configure_mem_clk_impl(_clocks: &mut ClockTree, _old: Option<MemClkConfig>, new: MemClkConfig) {
HP_SYS_CLKRST::regs()
.mem_freq_ctrl0()
.modify(|_, w| w.mem_clk_div_num().bit(new.divisor() == 1));
update_bus_clocks();
}

// SYS_CLK

fn enable_sys_clk_impl(_clocks: &mut ClockTree, _en: bool) {
// Nothing to do here
}

fn configure_ahb_clk_impl(_clocks: &mut ClockTree, _old: Option<AhbClkConfig>, new: AhbClkConfig) {
fn configure_sys_clk_impl(_clocks: &mut ClockTree, _old: Option<SysClkConfig>, new: SysClkConfig) {
HP_SYS_CLKRST::regs()
.sys_freq_ctrl0()
.modify(|_, w| unsafe {
Expand Down
12 changes: 8 additions & 4 deletions esp-metadata-generated/src/_build_script_utils.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -8157,8 +8157,10 @@ impl Chip {
"soc_clock_node_cpu_root_clk_is_configurable",
"soc_has_clock_node_cpu_clk",
"soc_clock_node_cpu_clk_is_configurable",
"soc_has_clock_node_ahb_clk",
"soc_clock_node_ahb_clk_is_configurable",
"soc_has_clock_node_mem_clk",
"soc_clock_node_mem_clk_is_configurable",
"soc_has_clock_node_sys_clk",
"soc_clock_node_sys_clk_is_configurable",
"soc_has_clock_node_apb_clk",
"soc_clock_node_apb_clk_is_configurable",
"soc_has_clock_node_lp_fast_clk",
Expand Down Expand Up @@ -8446,8 +8448,10 @@ impl Chip {
"cargo:rustc-cfg=soc_clock_node_cpu_root_clk_is_configurable",
"cargo:rustc-cfg=soc_has_clock_node_cpu_clk",
"cargo:rustc-cfg=soc_clock_node_cpu_clk_is_configurable",
"cargo:rustc-cfg=soc_has_clock_node_ahb_clk",
"cargo:rustc-cfg=soc_clock_node_ahb_clk_is_configurable",
"cargo:rustc-cfg=soc_has_clock_node_mem_clk",
"cargo:rustc-cfg=soc_clock_node_mem_clk_is_configurable",
"cargo:rustc-cfg=soc_has_clock_node_sys_clk",
"cargo:rustc-cfg=soc_clock_node_sys_clk_is_configurable",
"cargo:rustc-cfg=soc_has_clock_node_apb_clk",
"cargo:rustc-cfg=soc_clock_node_apb_clk_is_configurable",
"cargo:rustc-cfg=soc_has_clock_node_lp_fast_clk",
Expand Down
Loading
Loading