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#214 · enjoy-digital opened on Aug 3, 2020

AXI4 Full User Port Burst Mode Fails on LiteDRAM AXI2Native Bridge

#370

· gvillanovanm opened

on Oct 29, 2025

DDR4 Calibration Succeeds But Memtest Hangs Without Printf Statements

#369

· MojoJojo opened

on Oct 3, 2025

separate DDR and CPU clocks

#363

· juanschroeder opened

on May 4, 2025

Adding support to gowin phys in litedram.gen?

#357

· linhz0hz opened

on Apr 28, 2024

LiteDRAMDMAWriter sinks data when not enabled

#356

· DaveBerkeley opened

on Apr 24, 2024

Wishbone port does not accept more than one operation despite cmd_buffer_depth non-null in LiteDram yaml file,

#355

· fontamsoc opened

on Mar 30, 2024

GENDDRPHY support?

#353

· rhgndf opened

on Jan 20, 2024

litedram with vexriscv DDR4 SODIMM fails memtest (Xilinx VU9P + spd)

#349

· jersey99 opened

on Oct 5, 2023

Underclocking DRAM controler to increase access time

#346

· denishoornaert opened

on Aug 27, 2023

LiteDRAM core targeting DDR3 issues activate command twice for a write operation

#345

· dinaabdelbaky opened

on Aug 17, 2023

LiteDRAM DDR3 Core targeting Arty AXI read data appears on the Native port instead.

#344

· dinaabdelbaky opened

on Aug 17, 2023

Axi port write data error

#342

· Yuxin-Yu opened

on Jun 7, 2023