The STM32H753 linker script (modules/stm32/linkerscripts/stm32h753zi-sections.ld) binds _stm32_debug (and therefore stm32::h7xx::debug) to ORIGIN(PPB) + 0x42000 = 0xE0042000, which is the F4 DBGMCU address.
On STM32H7 the DBGMCU is not a CoreSight component:
- processor-core address:
0x5C001000
- debugger (APB-D) alias:
0xE00E1000
Consequence: Timer::Initialize() (modules/stm32/source/Timer2.cpp) sets timer2_stop_in_debug = 1, but the write lands on a dead address, so DBGMCU_APB1LFZ1.DBG_TIM2 never becomes 1 and TIM2 free-runs during debug halts. This corrupted all while-halted register/memory observations (TIM2 SR/CNT and the overflow counter), making the timer look grossly inaccurate when debugged.
Fix: set _stm32_debug = 0x5C001000;.
Verified on hardware:
stm32::h7xx::debug binds to 0x5C001000APB1LFZ1.DBG_TIM2 = 1 after boot- TIM2 now freezes with the core during debug; post-write SR=0x1E in the ISR confirms UIF clears correctly (clear-on-zero).
The STM32H753 linker script (
modules/stm32/linkerscripts/stm32h753zi-sections.ld) binds_stm32_debug(and thereforestm32::h7xx::debug) toORIGIN(PPB) + 0x42000=0xE0042000, which is the F4 DBGMCU address.On STM32H7 the DBGMCU is not a CoreSight component:
0x5C0010000xE00E1000Consequence:
Timer::Initialize()(modules/stm32/source/Timer2.cpp) setstimer2_stop_in_debug = 1, but the write lands on a dead address, soDBGMCU_APB1LFZ1.DBG_TIM2never becomes 1 and TIM2 free-runs during debug halts. This corrupted all while-halted register/memory observations (TIM2 SR/CNT and the overflow counter), making the timer look grossly inaccurate when debugged.Fix: set
_stm32_debug = 0x5C001000;.Verified on hardware:
stm32::h7xx::debugbinds to0x5C001000APB1LFZ1.DBG_TIM2 = 1after boot