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version 0.15.0 更新后遇到的跳转问题

Status: Open.

#282 In eirikpre/VSCode-SystemVerilog;

· yanxin20000908 opened on Jun 23, 2026

Line break problem after commenting under Chinese line breaks

Status: Open.

#252 In eirikpre/VSCode-SystemVerilog;

· xuttao opened on Feb 10, 2025

verible-verilog-format does not work correctly from VSCode-SystemVerilog

Status: Open.

#244 In eirikpre/VSCode-SystemVerilog;

· hwmland opened on Dec 10, 2024

Verilator problem matcher regex doesn't actually detect anything

Status: Open.

#231 In eirikpre/VSCode-SystemVerilog;

· alex-the-new-guy opened on Jul 18, 2024

Go to definition doesn't work for "spi" module name

Status: Open.

#227 In eirikpre/VSCode-SystemVerilog;

· hi0t opened on May 31, 2024

Syntax highlighting error

Status: Open.

#224 In eirikpre/VSCode-SystemVerilog;

· bbsbucket opened on Feb 21, 2024

Toggle Line Comment not working for Verilog Filelist?

Status: Open.

#223 In eirikpre/VSCode-SystemVerilog;

· musketon-be opened on Feb 15, 2024

Feature request, input/output signals use different colors

enhancementNew feature or requestNew feature or request

Status: Open.

#221 In eirikpre/VSCode-SystemVerilog;

· haimag opened on Jan 21, 2024

When instantiating, the signal can be listed in the form of wire

Status: Open.

#220 In eirikpre/VSCode-SystemVerilog;

· haidoph opened on Jan 19, 2024

SystemVerilog - Language Support - VCS linter

Status: Open.

#201 In eirikpre/VSCode-SystemVerilog;

· roinachum opened on Aug 14, 2023

Limit parsing when file count is greater than threshold

Status: Open.

#186 In eirikpre/VSCode-SystemVerilog;

· joecrop opened on Oct 9, 2022

Compile action doesn't work if file isn't within workspace

Status: Open.

#176 In eirikpre/VSCode-SystemVerilog;

· agg23 opened on Sep 6, 2022