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C extension support - #22

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Abdulwadoodd wants to merge 28 commits into
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dev/c-ext
Open

C extension support#22
Abdulwadoodd wants to merge 28 commits into
mainfrom
dev/c-ext

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@Abdulwadoodd

@Abdulwadoodd Abdulwadoodd commented Oct 30, 2023

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  • This is tested on top of fence.i fix.
  • All the required ACTs are passing
  • Uart hello example working.
  • Linux image running successfully in simulation

Edit:
The Linux kernel working on FPGA with C ext support
Fix: halt the icache request on tlb flush

Abdulwadoodd and others added 22 commits October 29, 2023 06:00
Implementation of state machine to handle mis-aligned memory access
that may arise due to Compressed instructions.

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Implement 16-bit to 32-bit decoder for Compressed Instructions

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
This incorporates instruction re-alignment and its decompression.
Only active whem Compressed Instruction encounters.

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
add `if_stall` and `comp_ack` to the interface.
These are used by pre-fetch interface for C inrtuctions

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
- Allow pc+2 increment in case Compressed instruction encounters
- stop mis-aligned memory access exception when half-word (pc+2) memory accessed.
- add if_stall signal to ICache interface for pre-fetch control

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
This is only active when Compressed Instruction encounters.
Otherwise, it will just pass through signals b/w IF and Icache.

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Make code style consistent with existing code base

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Compressed Extension Support in Pcore
arch-tests assumes that mtval should set with instruction address
on ebreak, however RISC-V privilege spec provide choice whether to set 0 or
faulty address in mtval.
This change is to make pcore consistent with ACTs.

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Fix: hello and linux example programs working with
compressed extension when simulated using verilator

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Updates the decompress module. Fix synthesis related errors of multi-driven signals

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Add extra state to avoid unncessary stalls when
switching from Compressed to Uncompressed instructions and
vice versa, when there is no flow control i.e branhc or jump

Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
Signed-off-by: Abdul Wadood <abdulwadood.afzal88@gmail.com>
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