YAVG — Yet Another Vortex GPGPU

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YAVG is an experimental GPGPU project based on SpinalHDL. It is primarily for learning GPGPU hardware architecture and exploring more efficient, flexible approaches to GPU design and iteration.

YAVG uses SpinalHDL plugins and pipelines to organize scheduling, decode, execution, and other functional units as composable modules. Individual units can be rearranged, replaced, or extended to support rapid exploration and implementation of different GPU architectures.

The default design draws on the Vortex GPGPU instruction-set extensions and SIMT microarchitecture, and supports running kernels written in a CUDA-like style.

ISA and SIMT model

YAVG uses a 32-bit, RISC-V-derived instruction base with Vortex-inspired SIMT control instructions.

The current implementation includes:

• integer arithmetic and logic operations;
• RV32M multiplication, division, and remainder operations;
• branches, jumps, and basic CSR operations;
• byte, halfword, and word loads and stores;
• SIMT control operations including TMC, WSPAWN, SPLIT, JOIN, and BAR.

Implementation

The default YAVG implementation is composed from the implementations below. Some modules can be replaced with experimental implementations through the same service interfaces to compare different architectural organizations and optimization approaches.

Function	Default implementation	Alternative or experimental implementation	Description
Pipeline organization	Schedule → Fetch → Decode → Issue → Execute	Additional or replacement execution plugins	The default core connects pipeline stages through pipeline nodes and services
Integer and control execution	Integer ALU, RV32M, control flow, warp control, divergence, barrier, and CSR plugins	Additional ExecutePlugin implementations	Each kind of execution logic is connected to the issue stage as an independent plugin
Register dependency tracking	BitmapWarpScoreboardPlugin	EntryBasedWarpScoreboardPlugin	The default implementation tracks pending writeback with a register bitmap; the entry-based implementation uses a fixed number of entries to record destination registers and thread masks
Register file	WarpRegfilePlugin	—	Each warp has an independent register file with per-thread register values
Memory access	SimpleLoadStorePlugin	CoalescedLoadStorePlugin	The default implementation provides a basic load/store path; the experimental implementation attempts to coalesce memory accesses within a warp
SIMT control flow	WarpDivergencePlugin	—	SPLIT, JOIN, and a per-warp reconvergence stack handle control-flow divergence

Quick start

Compile the project:

sbt compile

Generate the default Verilog top:

sbt "runMain yavg.rtl.YavgTopMain"

RTL simulation

Run simulations with Verilator through SpinalHDL:

sbt "testOnly yavg.core.CoreCases"
sbt "testOnly yavg.socket.SocketCases"
sbt "testOnly yavg.top.TopCases"

Run the full test suite with:

sbt test

Run kernel tests

Precompiled kernel images and their C sources are stored together under src/test/c/kernel/ and can be used directly for testing.

sbt 'testOnly yavg.top.TopCases -- -z "vectorAdd kernel"'
sbt 'testOnly yavg.top.TopCases -- -z "transpose kernel"'
sbt 'testOnly yavg.top.TopCases -- -z "sharedMemoryReduction kernel"'

Repository layout

src/
├── main/scala/yavg/
│   ├── rtl/         # SpinalHDL hardware implementation
│   ├── emu/         # Instruction-level reference model
│   ├── isa/         # Instruction definitions and execution models
│   └── test/        # Simulation cases, runners, and trace comparison
├── test/scala/yavg/ # ScalaTest suites
└── test/c/kernel/   # Small C kernel programs
fpga/
└── tang_console_138k/ # Experimental board bring-up flow

License

YAVG's original source code is licensed under Apache-2.0.

Acknowledgements

YAVG's main architecture and instruction set draw on the Vortex GPGPU project.

YAVG is implemented with SpinalHDL. Its composable plugin, fiber, and pipeline structure draws inspiration from projects such as NaxRiscv and VexiiRiscv.